NB6L11M 데이터 시트보기 (PDF) - ON Semiconductor
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NB6L11M Datasheet PDF : 9 Pages
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NB6L11M
VCC VEE VEE VCC Exposed Pad (EP)
16 15 14 13
VTD 1
D2
D3
VTD 4
NB6L11M
12 Q0
11 Q0
10 Q1
9 Q1
5678
VCC VREFAC VEE VCC
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1
VTD
−
Internal 50 W Termination Pin for D input.
2
D
ECL, CML,
Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
LVCMOS, LVDS,
LVTTL Input
3
D
ECL, CML,
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
LVCMOS, LVDS,
LVTTL Input
4
VTD
−
Internal 50 W Termination Pin for D input.
5
VCC
6
VREFAC
7
VEE
8
VCC
9
Q1
10
Q1
11
Q0
12
Q0
13
VCC
14
VEE
15
VEE
16
VCC
−
EP
−
−
−
CML Output
CML Output
CML Output
CML Output
−
−
−
−
−
Positive Supply Voltage
Output Reference Voltage for direct or capacitor coupled inputs
Negative Supply Voltage
Positive Supply Voltage
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
Positive Supply Voltage
Negative Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation.
2. All VCC and VEE pins must be externally connected to a power supply for proper operation.
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