NB6L14(2007) 데이터 시트보기 (PDF) - ON Semiconductor
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NB6L14 Datasheet PDF : 10 Pages
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NB6L14
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40°C to +85°C (Note 9)
Symbol
Characteristic
Min
Typ
VOUTPP
Output Voltage Amplitude (@ VINPPmin) (Note 10)
fIN ≤ 1.25 GHz
550
700
1.25 GHz ≤ fin ≤ 2.0 GHz
380
500
2.0 GHz ≤ fin ≤ 3.0 GHz
250
320
fDATA
Maximum Operating Data Rate
2.5
tPD
Propagation Delay
IN to Q
350
tS
Set-Up Time (Note 11)
EN to IN, IN
300
tH
Hold Time (Note 11)
EN to IN, IN
300
tSKEW
Within-Device Skew (Note 12)
5.0
Device to Device Skew (Note 13)
tJITTER
RMS Random Jitter (Note 14)
Peak-to-Peak Data Dependent Jitter
fIN = 2.5 GHz
(Note 15)
fDATA = 2.5 Gb/s
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VINPP
Input Voltage Swing/Sensitivity
100
(Differential Configuration) (Note 10)
tr,tf
Output Rise/Fall Times @ Full Output Swing
(20%-80%)
70
150
Max
20
150
1.0
VCC - GND
200
Unit
mV
Gb/s
ps
ps
ps
ps
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPP (min) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC – 2.0 V. Input edge
rates 40 ps (20%-80%).
10. Input and output voltage swing is a single-ended measurement operating in differential mode.
11. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold times do not apply.
12. Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2^23-1 and K28.5 at 2.5Gb/s.
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