NBC12439 데이터 시트보기 (PDF) - ON Semiconductor

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NBC12439

3.3V/5V Programmable PLL Synthesized Clock Generator

ON Semiconductor 

NBC12439, NBC12439A

Most of the signals available on the TEST output pin are

useful only for performance verification of the device itself.

However, the PLL bypass mode may be of interest at the

board level for functional debug. When T[2:0] is set to 110,

the device is placed in PLL bypass mode. In this mode the

S_CLOCK input is fed directly into the M and N dividers.

The N divider drives the FOUT differential pair and the M

counter drives the TEST output pin. In this mode the

S_CLOCK input could be used for low speed board level

functional test or debug. Bypassing the PLL and driving

FOUT directly gives the user more control on the test clocks

sent through the clock tree. Figure 7 shows the functional

setup of the PLL bypass mode. Because the S_CLOCK is a

CMOS level the input frequency is limited to 250 MHz or

less. This means the fastest the FOUT pin can be toggled via

the S_CLOCK is 250 MHz as the minimum divide ratio of

the N counter is 1. Note that the M counter output on the

TEST output will not be a 50% duty cycle due to the way the

divider is implemented.

T2

T1

0

0

0

0

0

1

0

1

1

0

1

0

1

1

1

1

T0

TEST OUTPUT

0

SHIFT REGISTER OUT

1

HIGH

0

FREF

1

M COUNTER OUT

0

FOUT

1

LOW

0

PLL BYPASS

1

FOUT ÷ 4

M[6:0]

N[1:0]

P_LOAD

VALID

ts

th M, N to P_LOAD

Figure 5. Parallel Interface Timing Diagram

S_CLOCK

S_DATA

S_LOAD

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12

ts

th S_DATA to S_CLOCK

T2 T1 T0 N1 N0 M6 M5 M4 M3 M2 M1 M0

First

Last

Bit

Bit

th

ts

S_CLOCK to S_LOAD

Figure 6. Serial Interface Timing Diagram

FREF_EXT

MCNT

PLL 12430

SCLOCK

VCO_CLK

0

N÷

FOUT

1

(1, 2, 4, 8) (VIA ENABLE GATE)

SDATA

M COUNTER

FDIV4

MCNT

7

SHIFT

REG T0

14--BIT T1

T2

LATCH

Reset

SLOAD

PLOAD

DECODE

LOW

FOUT

MCNT

FREF

HIGH

TEST

MUX

0

• T2=T1=1, T0=0: Test Mode

• SCLOCK is selected, MCNT is on TEST output, SCLOCK ÷ N is on FOUT pin.

PLOAD acts as reset for test pin latch. When latch reset, T2 data is shifted out TEST pin.

Figure 7. Serial Test Clock Block Diagram

TEST

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