NCV4299(2009) 데이터 시트보기 (PDF) - ON Semiconductor

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NCV4299
(Rev.:2009)

150 mA Low-Dropout Voltage Regulator

ON Semiconductor 

NCV4299

Reset Output (RO)

A reset signal, Reset Output (RO, low voltage) is

generated as the IC powers up. After the output voltage VQ

increases above the reset threshold voltage VRT, the delay

timer D is started. When the voltage on the delay timer VD

passes VUD, the reset signal RO goes high. A discharge of

the delay timer (VD) is started when VQ drops and stays

below the reset threshold voltage VRT. When the voltage of

VI

the delay timer (VD) drops below the lower threshold

voltage VLD, the reset output voltage VRO is brought low to

reset the processor.

The reset output RO is an open collector NPN transistor,

controlled by a low voltage detection circuit. The circuit is

functionally independent of the rest of the IC, thereby

guaranteeing that RO is valid for VQ as low as 1.0 V.

VQ

VRT

VD

VUD

VLD

td

tRR

VRO

t

< tRR

t

dV

dt

+

ID

CD

t

VRO,SAT

t

Power−on−Reset

Thermal

Shutdown

Voltage Dip

at Input

Undervoltage

Secondary

Spike

Figure 41. Reset Timing Diagram

Overload

at Output

Reset Adjust (RADJ)

The reset threshold VRT can be decreased from a typical

value of 4.64 V to as low as 3.5 V by using an external

voltage divider connected from the Q lead to the pin RADJ,

as shown in Figures 39 and 40. The resistor divider keeps the

voltage above the VRADJ,TH, (typ. 1.36 V), for the desired

input voltages and overrides the internal threshold detector.

Adjust the voltage divider according to the following

relationship:

VTHRES + VRADJ, TH · (RADJ1 ) RADJ2)ńRADJ2

(eq. 1)

If the reset adjust option is not needed, the RADJ−pin

should be connected to GND causing the reset threshold to

go to its default value (typ. 4.64 V).

Reset Delay (D)

The reset delay circuit provides a delay (programmable by

capacitor CD) on the reset output RO lead. The delay lead D

provides charge current ID (typically 7.1 mA) to the external

delay capacitor CD during the following times:

1. During Powerup (once the regulation threshold has

been exceeded).

2. After a reset event has occurred and the device

is back in regulation. The delay capacitor is

set to discharge when the regulation (VRT, reset

threshold voltage) has been violated. When

the delay capacitor discharges to down to VLD,

the reset signal RO pulls low.

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