NCV4299(2009) 데이터 시트보기 (PDF) - ON Semiconductor

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NCV4299
(Rev.:2009)

150 mA Low-Dropout Voltage Regulator

ON Semiconductor 

NCV4299

Setting the Delay Time

The delay time is set by the delay capacitor CD and the

charge current ID. The time is measured by the delay

capacitor voltage charging from the low level of VD,sat to the

higher level VUD. The time delay follows the equation:

td + [CD (VUD−VD, sat)]ńID

(eq. 2)

Example:

Using CD = 100 nF.

Use the typical value for VD,sat = 0.1 V.

Use the typical value for VUD = 1.85 V.

Use the typical value for Delay Charge Current ID = 7.1 mA.

td + [100 nF(1.85−0.1 V)]ń7.1 mA + 24.6 ms (eq. 3)

When the output voltage VQ drops below the reset

threshold voltage VRT, the voltage on the delay capacitor VD

starts to drop. The time it takes to drop below the lower

threshold voltage of VLD is the reset reaction time, tRR. This

time is typically 2.2 ms for a delay capacitor of 0.1 mF. The

reset reaction time can be estimated from the following

relationship:

tRR + 22 nsńnF CD

(eq. 4)

Sense Input (SI)/Sense Output (SO) Voltage Monitor

An on−chip comparator is available to provide early

warning to the microprocessor of a possible reset signal. The

reset signal typically turns the microprocessor off

instantaneously. This can cause unpredictable results with

the microprocessor. The signal received from the SO pin will

allow the microprocessor time to complete its present task

before shutting down. This function is performed by a

comparator referenced to the band gap voltage. The actual

trip point can be programmed externally using a resistor

divider to the input monitor (SI) (Figures 39 and 40). The

typical threshold is 1.35 V on the SI Pin.

Signal Output

Figure 42 shows the SO Monitor waveforms as a result of

the circuits depicted in Figures 39 and 40. As the output

voltage VQ falls, the monitor threshold VSI,Low is crossed.

This causes the voltage on the SO output to go low sending

a warning signal to the microprocessor that a reset signal may

occur in a short period of time. TWARNING is the time the

microprocessor has to complete the function it is currently

working on and get ready for the reset shutdown signal.

Sense

Input

Voltage

VQ

VSI,High

VSI

VSI,Low

VRO

VSO

VSI,Low

Sense

Output

High

tPSOLH

t

tPSOHL

TWARNING

Figure 42. SO Warning Timing Waveform

Calculating Power Dissipation in a Single Output

Linear Regulator

The maximum power dissipation for a single output

regulator is:

PD(max) + [VI(max)−VQ(min)] IQ(max) ) VI(max)Iq

(eq. 5)

where:

VI(max) is the maximum input voltage,

VQ(min) is the minimum output voltage,

IQ(max) is the maximum output current for the application,

and

Low

t

Figure 43. Sense Timing Diagram

Iq is the quiescent current the regulator consumes at IQ(max).

Once the value of PD(max) is known, the maximum

permissible value of RqJA can be calculated:

RqJA + (150° C−TA)ńPD

(eq. 6)

The value of RqJA can then be compared with those in the

package section of the data sheet. Those packages with

RqJA’s less than the calculated value in Equation 6 will keep

the die temperature below 150°C. In some cases, none of the

packages will be sufficient to dissipate the heat generated by

the IC, and an external heatsink will be required.

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