NJU6680 데이터 시트보기 (PDF) - Japan Radio Corporation

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NJU6680

128-common x 128-segment 4-level Gray Scale BITMAP LCD DRIVER

Japan Radio Corporation  

NJU6680

(1-9) LCD display circuits

(a) Common and segment drivers

The common and segment drivers are used to generate LCD driving waveforms in accordance with the

combination of display data, common timing signal (CL) and internal frame signal (FL).

(b) Display timing generator

The display timing generator is used to generate the common timing signal (CL) and the internal frame

signal (FR). The FR signal adopts the 2-frame AC driving method, in which the FR signal is toggled to

alternate the crystal polarization on an LCD panel. It toggles on every frame in the default setting or once

every N frames in the N-line inversion mode setting, as illustrated in Fig.2-1 and Fig.2-2.

(c) Display Data Latch Circuit

The display data latch circuit is used to temporally store the 128-bit display data transferred from the

DDRAM and output these display data onto the segment drivers in synchronization of the CL signal. The

output timing for the display data, from display latch circuits to segment drivers, is independent of the

access timing from MPU to DDRAM. As a result, the LCD display is not affected by the DDRAM access.

The “Display ON/OFF”, “Reverse display ON/OFF” and “Entire display ON/OFF” instructions control the

display data in the display data latch circuit, however they do not change the display data in the DDRAM.

127 128 1 2 3 4 5 6 7 8 9 10 11 12 13

CL

FR

127 128 1 2 3 4 5 6 7 8 9 10 11 12 13

COM0

COM1

SEGn

Duty cycle ratio=1/128

Fig.2-1 LCD driving Waveforms

Ver.2003-04-08

- 13 -

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