NT5SV16M16AT 데이터 시트보기 (PDF) - Unspecified

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NT5SV16M16AT

256Mb Synchronous DRAM

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NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

Burst write operations will be terminated by the Precharge command. The last write data that will be properly stored in the

device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the

Data-in to Precharge delay, tDPL.

Precharge Termination of a Burst Write

(Burst Length = 8, CAS Latency = 2, 3)

T0

T1

T2

T3

T4

T5

T6

T7

T8

CK

COMMAND NOP

NOP

WRITE Ax0

NOP

NOP

NOP

Precharge A

NOP

NOP

DQM

CAS latency = 2

tCK2, DQs

CAS latency = 3

tCK3, DQs

tDPL ‡

DIN Ax0

DIN Ax 1

DIN Ax2

DIN Ax0

DIN Ax 1

tDPL‡

DIN Ax2

‡ tDPL is an asynchronous timing and may be completed in one or two clock cycles

depending on clock cycle time.

REV 1.0

May, 2001

24

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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