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NTE1690

Integrated Circuit Telephone DTMF Dialer

NTE Electronics 

Electrical Characteristics (Cont’d): (–30°C < TA < +60°C, 3V < VDD < 10V unless othewise specified)

Parameter

Test Conditions Min Typ Max Unit

Input Resistors

COLUMN and ROW (Pull–Up)

– 40 –

kΩ

SINGLE TONE INHIBIT (Pull–Down)

– 50 –

kΩ

TONE DISABLE (Pull–Up)

– 50 –

kΩ

MUTE OUT Sink Current (COLUMN and ROW Active)

Output Amplitudes, Low Group

Output Amplitudes, High Group

Mean Output DC Offset

High Group Pre–Emphasis

VDD = 3V, VO = 0.5V 0.5 –

– mA

RL = 240Ω, VDD = 3V – 250 – mVrms

RL = 240Ω, VDD = 10V – 850 – mVrms

RL = 240Ω, VDD = 3V – 315 – mVrms

RL = 240Ω, VDD = 10V – 1000 – mVrms

VDD = 3V

– 1.2 –

V

VDD = 10V

– 4.2 –

V

2.4 2.7 3.0 dB

Dual Tone/Harmonic Distortion Ratio

1MHz Bandwidth

22 –

–

dB

Start–Up Time (90% Amplitude)

–

3

5

ms

Note 1. Crystal Specification: Parallel Resonant 3.579545MHz, RS ≤ 150Ω, L = 100mH, C0 = 5pF,

C1 = 0.02pf.

Pin Descriptions:

VDD (Pin1): This is the positive voltage supply to the device, referenced to VSS. The collector of the

TONE OUT transistor is connected to this pin.

VSS (Pin6): This is the negative voltage supply.

OSCILLATOR (Pin7 and Pin8): All tone generation timing is derived from the on–chip oscillator cir-

cuit. A low–cost 3.579545MHz A–cut crystal (NTSC TV color–burst) is needed between Pin7 and

Pin8. Load capacitors and feedback resistor are included on–chip for good start–up and stability.

The oscillator stops when column inputs are sensed with no valid input having been detected. The

oscillator is also stopped when the TONE DISABLE input is pulled to logic low.

Row and Column Inputs (Pins 3, 4, 5, 9, 11, 12, 13, 14): When no key is pushed, pull–up resistors

are active on row and column inputs. A key closure is recognized when a single row and a single

column are connected to VSS, which starts the oscillator and initiates tone generation. Negative–true

logic signals simulating key closures can also be used.

TONE DISABLE Input (Pin2): The TONE DISABLE input has an internal pull–up resistor. When this

input is open or at logic high, the normal tone output mode will occur. When TONE DISABLE input

is at logic low, the device will be in the inactive mode, TONE OUTPUT will be at an open circuit state.

MUTE Output (Pin10): The MUTE output is an open–drain N–channel device that sinks current to

VSS with any key input and is open when no key input is sensed. The MUTE output will switch regard-

less o the state of he SINGLE TONE INHIBIT input.

SINGLE TONE INHIBIT Input (Pin15): The SINGLE TONE INHIBIT input is used to inhibit the gener-

ation of other than valid tone pairs due to multiple row–column closures. It has a pull–down resistor

to VSS, and when left open or tied to VSS any input condition that would normally result in a single tone

will now result in no tone, with all other functions operating normally. When tied to VDD, single or dual

tones may be generated (See Table II).

TONE OUT (Pin16): This output is the open emitter of an NPN transistor, the collector of which is

connected to VDD. When an external load resistor is connected from TONE OUT to VSS, the output

voltage on this pin is the sum of the high and low group sine–waves superimposed on a DC offset.

When not generating tones, this output transistor is turned OFF to minimize the device idle current.

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