OM6211 데이터 시트보기 (PDF) - Philips Electronics

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OM6211

48×84 dot matrix LCD driver

Philips Electronics 

Philips Semiconductors

48 × 84 dot matrix LCD driver

Product specification

OM6211

9.1 Reset

The OM6211 has no internal Power-on reset, only external

reset and reset by command. After power-on an external

reset is required. A reset initiated either from the RES pin

or by command will initialize the chip to the following

starting conditions:

• Power-down mode (DON = 0 and DAL = 1):

– Internal oscillator stopped

– The VLCD generator (HV generator) is switched off

(HVE = 0) and VLCDOUT is 3-state

– Display is off and all LCD outputs are internally

connected to VSS (DON = 0)

– Display all points is on (DAL = 1).

• Serial interface initialized; write mode

• Display normal video (E = 0)

• Address counter X6 to X0 = 0; Y2 to Y0 = 0; display start

line Z5 to Z0 = 0; no Y mirroring (MY = 0)

• Bias system 1⁄7 (BS2 to BS0 = 100)

• VLCD selection VPR7 to VPR0 = 0

• Voltage multiplication factor 4 (S1 and S0 = 10)

• Temperature control mode TC3 (TC1 and TC0 = 11)

• Frequency not calibrated and OC = 0

• RAM data is unchanged (after power-up undefined).

9.3 LCD voltage selector

The practical value for VLCD is determined by equating

Voff(rms) with a defined LCD threshold voltage (Vth),

typically when the LCD exhibits approximately 10%

contrast.

9.4 Oscillator

The internal logic operation and the multi-level drive

signals of the OM6211 are clocked by the built-in RC

oscillator. No external components are required. The

oscillator is in operation as long as the chip is not in

Power-down mode.

9.5 Timing

The timing of the OM6211 organizes the internal data flow

of the device. The timing also generates the LCD frame

frequency that is derived from the clock frequency

generated by the internal clock generator.

9.6 Column driver outputs

The LCD drive section includes 84 column outputs, which

should be connected directly to the LCD. The column

output signals are generated in accordance with the

multiplexed row signals and with the data in the display

latch. If less than 84 columns are required, the unused

column outputs should be left open-circuit.

9.2 Power-down

The chip is in Power-down mode if the display is off

(DON = 0) and display all points is on (DAL = 1),

regardless of the order in which both bits are set. During

the Power-down mode almost all static currents are

switched off (no internal oscillator, no timing and no LCD

segment drive system), and all LCD outputs are internally

connected to VSS. The VLCD generator is switched off (but

HVE is not affected). The serial interface function remains.

RAM data is unchanged. When exiting the Power-down

mode, the VOS value is stored in a register.

9.7 Row driver outputs

The LCD drive section includes 48 row outputs, which

should be connected directly to the LCD. If less than

48 rows are required, the unused row outputs should be

left open-circuit.

2002 Jan 17

8

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