DS1010-100 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

부품명

상세내역

제조사

DS1010-100

10-Tap Silicon Delay Line

Dallas Semiconductor -> Maxim Integrated 

TEST CIRCUIT Figure 3

DS1010

TERMINOLOGY

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the

following pulse.

tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the

1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading

edge.

tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the

input pulse.

tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the

input pulse.

tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input

pulse and the 1.5V point on the leading edge of any tap output pulse.

tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input

pulse and the 1.5V point on the trailing edge of any tap output pulse.

5 of 6

Share Link: