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OR2C-2T04A

ORCA® Series 2 Field-Programmable Gate Arrays

Unspecified 

Data Sheet

June 1999

ORCA Series 2 FPGAs

FPGA States of Operation (continued)

VDD

RESET

PRGM

INIT

M[3:0]

CCLK

HDC

LDC

DONE

USER I/O

INTERNAL

RESET

(gsm)

INITIALIZATION

CONFIGURATION

START-UP

OPERATION

Figure 37. Initialization/Configuration/Start-Up Waveforms

5-4482(F)

All OR2CxxA I/Os operate as TTL inputs during config-

uration (OR2TxxA/OR2TxxB I/Os are CMOS-only). All

I/Os that are not used during the configuration process

are 3-stated with internal pull-ups. During configura-

tion, the PLC latch/FFs are held set/reset and the inter-

nal BIDI buffers are 3-stated. The TRIDIs in the PICs

are not 3-stated. The combinatorial logic begins to

function as the FPGA is configured. Figure 37 shows

the general waveform of the initialization, configuration,

and start-up states.

Configuration

The ORCA Series FPGA functionality is determined by

the state of internal configuration RAM. This configura-

tion RAM can be loaded in a number of different

modes. In these configuration modes, the FPGA can

act as a master or a slave of other devices in the sys-

tem. The decision as to which configuration mode to

use is a system design issue. The next section dis-

cusses configuration in detail, including the configura-

tion data format and the configuration modes used to

load the configuration data in the FPGA.

Lucent Technologies Inc.

41

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