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OR2C-2T04A

ORCA® Series 2 Field-Programmable Gate Arrays

Unspecified 

ORCA Series 2 FPGAs

Data Sheet

June 1999

FPGA Configuration Modes (continued)

Master Serial Mode

In the master serial mode, the FPGA loads the configu-

ration data from an external serial ROM. The configura-

tion data is either loaded automatically at start-up or on

a PRGM command to reconfigure. The ATT1700 and

ATT1700A Series can be used to configure the FPGA

in the master serial mode. This provides a simple 4-pin

interface in an 8-pin package. The ATT1736, ATT1765,

and ATT17128 serial ROMs store 32K, 64K, and 128K

bits, respectively.

Configuration in the master serial mode can be done at

powerup and/or upon a configure command. The sys-

tem or the FPGA must activate the serial ROM's

RESET/OE and CE inputs. At powerup, the FPGA and

serial ROM each contain internal power-on reset cir-

cuitry that allows the FPGA to be configured without

the system providing an external signal. The power-on

reset circuitry causes the serial ROM's internal address

pointer to be reset. After powerup, the FPGA automati-

cally enters its initialization phase.

The serial ROM/FPGA interface used depends on such

factors as the availability of a system reset pulse, avail-

ability of an intelligent host to generate a configure

command, whether a single serial ROM is used or mul-

tiple serial ROMs are cascaded, whether the serial

ROM contains a single or multiple configuration pro-

grams, etc. Because of differing system requirements

and capabilities, a single FPGA/serial ROM interface is

generally not appropriate for all applications.

Data is read in the FPGA sequentially from the serial

ROM. The DATA output from the serial ROM is con-

nected directly into the DIN input of the FPGA. The

CCLK output from the FPGA is connected to the

CLOCK input of the serial ROM. During the configura-

tion process, CCLK clocks one data bit on each rising

edge.

Since the data and clock are direct connects, the

FPGA/serial ROM design task is to use the system or

FPGA to enable the RESET/OE and CE of the serial

ROM(s). There are several methods for enabling the

serial ROM’s RESET/OE and CE inputs. The serial

ROM's RESET/OE is programmable to function with

RESET active-high and OE active-low or RESET active-

low and OE active-high.

In Figure 41, serial ROMs are cascaded to configure

multiple daisy-chained FPGAs. The host generates a

500 ns low pulse into the FPGA's PRGM input. The

FPGA’s INIT input is connected to the serial ROM’s

RESET/OE input, which has been programmed to

function with RESET active-low and OE active-high.

48

The FPGA DONE is routed to the CE pin. The low on

DONE enables the serial ROMs. At the completion of

configuration, the high on the FPGA's DONE disables

the serial ROM.

Serial ROMs can also be cascaded to support the con-

figuration of multiple FPGAs or to load a single FPGA

when configuration data requirements exceed the

capacity of a single serial ROM. After the last bit from

the first serial ROM is read, the serial ROM outputs

CEO low and 3-states the DATA output. The next serial

ROM recognizes the low on CE input and outputs con-

figuration data on the DATA output. After configuration

is complete, the FPGA’s DONE output into CE disables

the serial ROMs.

This FPGA/serial ROM interface is not used in applica-

tions in which a serial ROM stores multiple configura-

tion programs. In these applications, the next

configuration program to be loaded is stored at the

ROM location that follows the last address for the previ-

ous configuration program. The reason the interface in

Figure 41 will not work in this application is that the low

output on the INIT signal would reset the serial ROM

address pointer, causing the first configuration to be

reloaded.

In some applications, there can be contention on the

FPGA's DIN pin. During configuration, DIN receives

configuration data, and after configuration, it is a user

I/O. If there is contention, an early DONE at start-up

(selected in ORCA Foundry) may correct the problem.

An alternative is to use LDC to drive the serial ROM's

CE pin. In order to reduce noise, it is generally better to

run the master serial configuration at 1.25 MHz (M3 pin

tied high), rather than 10 MHz, if possible.

DATA

CLK

ATT1700A

CE

RESET/OE

CEO

DATA

CLK

ATT1700A

CE

RESET/OE

CEO

DIN

CCLK

DOUT

TO DAISY-

CHAINED

DEVICES

DONE

INIT

ORCA

SERIES

FPGA

PRGM

M2

M1

M0

TO MORE

SERIAL ROMs

AS NEEDED

PROGRAM

5-4456.1(F)

Figure 41. Master Serial Configuration Schematic

Lucent Technologies Inc.

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