OX16PCI952-TQFP-A 데이터 시트보기 (PDF) - Unspecified
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OX16PCI952-TQFP-A
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OX16PCI952-TQFP-A Datasheet PDF : 76 Pages
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OXFORD SEMICONDUCTOR LTD.
OX16PCI952
1 PERFORMANCE COMPARISON
Feature
Internal serial channels
Integral 1284 Compliant parallel port
Multi- function PCI device
Support for PCI Power Management
Zero wait-state read/write operation
No. of available external interrupt pins
DWORD access to UART Interrupt Source
Registers & FIFO Levels
Good-Data status
Full Plug and Play with external EEPROM
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16PCI952
2
yes
yes
yes
yes
2
yes
yes
yes
yes
15 Mbps
60 Mbps
128
yes
yes
yes
yes
128
128
128
yes
yes
yes
248
yes
yes
yes
yes
yes
yes
16C552 + PCI
Bridge
0
no
no
no
no
2
no
no
yes
no
115 Kbps
n/a
16
no
no
no
no
4
1
n/a
no
no
no
n/a
no
no
no
no
no
no
16C652 + PCI
Bridge
0
no
no
no
no
2
no
no
yes
no
1.5 Mbps
n/a
64
yes
yes
yes
no
4
4
4
no
no
no
2
no
no
no
no
no
yes
Table 1: OX16PCI952 performance compared with PCI Bridge + generic UART/Parallel Port Combinations.
1.1 Improvements of the OX16PCI952 over discrete solutions:
Higher degree of integration:
The OX16PCI952 offers two internal ultra-high
performance 16C950 UARTs and one IEEE1284 compliant
bi-directional parallel port.
UART device driver efficiency is increased by using each
channel’s features such as the 128-byte deep transmitter &
receiver FIFOs, flexible clock options, automatic flow
control, programmable interrupt and flow control trigger
levels and readable FIFO levels. Data rates of each UART
is up to 60Mbps.
DataSheet Revision 1.1
Improved access timing:
Access to the internal UARTs require zero or one PCI wait
states. A PCI read transaction from an internal UART can
complete within five PCI clock cycles and a write
transaction to an internal UART can complete within four
PCI clock cycles.
Reduces interrupt latency:
The OX16PCI952 offers shadowed FIFO levels and
Interrupt status registers of the internal UARTs, as well as
general device interrupt status, to reduce the device driver
interrupt latency.
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