OX16PCI952-TQFP-A 데이터 시트보기 (PDF) - Unspecified

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OX16PCI952-TQFP-A

Integrated High Performance Dual UARTs, Parallel Port and 5.0v PCI interface

Unspecified 

OXFORD SEMICONDUCTOR LTD.

OX16PCI952

Pins

Serial port pins (Contd)

106

96

109

99

Dir1

Name

I

DCD[0]#

I

DCD[1]#

O

DTR[0]#

O

DTR[1]#

109

O

485_En[0]

99

O

485_En[1]

109

O

Tx_Clk_Out[0]

99

O

Tx_Clk_Out[1]

110

O

RTS[0]#

100

O

RTS[1]#

108

I

CTS[0]#

98

I

CTS[1]#

107

I

DSR[0]#

97

I

DSR[1]#

107

97

105

95

105

95

DataSheet Revision 1.1

I

Rx_Clk_In[0]

I

Rx_Clk_In[0]

I

RI[0]#

I

RI[1]#

I

Tx_Clk_In[0]

I

Tx_Clk_In[0]

Description

Active-low modem “data-carrier-detect” input, for UART 0

and UART 1.

Active-low modem “data-terminal-ready output”, for UART 0

and UART 1.

If automated DTR# flow control is enabled for the

corresponding UART channel, the DTR# pin is asserted and

deasserted if the receiver FIFO reaches or falls below the

channel’s programmed thresholds, respectively.

In RS485 half-duplex mode, the DTR# pin of each UART

channel may be programmed to reflect the sta te of the

channel’s transmitter empty bit to automatically control the

direction of the RS485 transceiver buffer (see register

ACR[4:3])

Transmitter 1x clock (baud rate generator output).

For isochronous applications, the 1x (or Nx) transmitter clock

of each UART channel may be asserted on the DTR# pins

(see register CKS[5:4])

Active-low modem “request-to-send” output, for UART 0 and

UART 1.

If automated RTS# flow control is enabled for the

corresponding UART channel, the RTS# pin is deasserted

and reasserted whenever the receiver FIFO reaches or falls

below the programmed thresholds, respectively.

Active-low modem “clear-to-send” input, for UART 0 and

UART 1.

If automated CTS# flow control is enabled for the

corresponding UART channel, upon deassertion of the CTS#

pin, the channel’s transmitter will complete the current

character and enter the idle mode until the CTS# pin is

reasserted. Note: flow control characters are transmitted

regardless of the state of the CTS# pin.

Active-low modem “data-set-ready” input, for UART 0 and

UART 1.

If automated DSR# flow control is enabled for the

corresponding UART channel, upon deassertion of the

channel’s DSR# pin, the transmitter will complete the current

character and enter the idle mode until the DSR# pin is

reasserted. Note: flow control characters are transmitted

regardless of the state of the DSR# pin

External receiver clock input, for isochronous applications.

The DSR Uart pins are redefined as Rx_Clk_In, when the

corresponding UART channel’s CKS[1:0] register bits = ‘01’.

Active-low modem “Ring-Indicator” input, for UART 0 and

UART 1.

External transmitter clock.

The RI Uart pins are redefined as transmitter clk pins (and

thus used indirectly by the receiver) when the UART

channel’s CKS[6] register bit =’1’.

Page 9

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