NT7502H-TABF1 데이터 시트보기 (PDF) - Novatek Microelectronics
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NT7502H-TABF1 Datasheet PDF : 54 Pages
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NT7502
Functional Description
Microprocessor Interface
Interface type selection
The NT7502 can transfer data via 8-bit bi-directional data bus (D7 to D0) or via serial data input (SI). When high or low is
selected for the parity of P/S pad, either 8-bit parallel data input or serial data input can be selected as shown in Table 1. When
serial data input is selected, the RAM data cannot be read out.
Table. 1
P/S
Type
CS1
CS2
A0
RD
WR
C86
D7
D6 D0 to D5
H
Parallel Input CS1
CS2
A0
RD
WR
C86
D7
D6 D0 to D5
L
Serial Input
CS1
CS2
A0
-
-
-
SI
SCL
(HZ)
“-” Must always be high or low
Parallel Input
When the NT7502 selects parallel input (P/S = high), the 8080 series microprocessor or 6800 series microprocessor can be
selected by causing the c86 pad to go high or low as shown in Table 2.
Table. 2
C86
Type
CS1
CS2
A0
RD
WR
H 6800 microprocessor bus CS1
CS2
A0
E
R/ W
L
8080 microprocessor bus
CS1
CS2
A0
RD
WR
D0 to D7
D0 to D7
D0 to D7
Data Bus Signals
The NT7502 identifies the data bus signal according to A0, E, R / W ( RD , WR ) signals.
Table. 3
Common
A0
1
1
0
0
6800 processor
(R/W )
1
0
1
0
8080 processor
RD
WR
0
1
1
0
0
1
1
0
Function
Reads display data
Writes display data
Reads status
Writes control data in internal register. (Command)
Serial Interface (P/S is low)
When the serial interface has been selected (P/S = “L”), then when the chip is in active state ( CS1 = “L” and CS2 = “H”), the
serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the
rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits of parallel data in the rising edge
of eighth serial clock for processing.
The A0 input is used to determine whether or the serial data input is display data, and when A0 = “L” then the data is command
data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active.
Figure 1 is the serial interface signal chart.
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