T431616A-7C 데이터 시트보기 (PDF) - Taiwan Memory Technology

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T431616A-7C

1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

T431616A

OPERATING AC PARAMETER

(AC opterating conditions unless otherwise noted)

Parameter

Symbol

Row active to row active delay

tRRD(min)

RAS to CAS delay

tRCD(min)

Row precharge time

tRP(min)

Row active time

tRAS(min)

tRAS(max)

Row cycle time

tRC(min)

Last data in to new col. Address delay tCDL(min)

Last data in to row precharge

tRDL(min)

Last data in to burst stop

tBDL(min)

Col. Address to col. Address delay

Number of valid output data

tCCD(min)

CAS latency=3

CAS latency=2

Speed Version

-6 -7 -8 -10

12 14 16 20

16 16 20 20

18 20 20 20

42 42 48 50

100K

60 63 68 70

1

2

1

1

1

1

Unit

ns

ns

ns

ns

ns

ns

CLK

CLK

CLK

CLK

ea

Note

1

1

1

1

1

2

2

2

3

4

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required

with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is

CL + BL-2 clocks.

Taiwan Memory Technology, Inc. reserves the right P. 8

to change products or specifications without notice.

Publication Date: DEC. 2000

Revision: C

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