M74HCT165TTR 데이터 시트보기 (PDF) - STMicroelectronics

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M74HCT165TTR

8 BIT PISO SHIFT REGISTER

STMicroelectronics 

M74HCT165

8 BIT PISO SHIFT REGISTER

s HIGH SPEED :

tPD = 26ns (TYP.) at VCC = 4.5V

s LOW POWER DISSIPATION:

ICC =4µA(MAX.) at TA=25°C

s COMPATIBLE WITH TTL OUTPUTS :

VIH = 2V (MIN.) VIL = 0.8V (MAX)

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 165

DESCRIPTION

The M74HCT165 is an high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated with silicon

gate C2MOS technology.

This device contains eight clocked master slave

RS flip-flops connected as a shift register, with

auxiliary gating to provide over-riding

asynchronous parallel entry. Parallel data enters

when the shift/load input is low. The parallel data

can change while shift/load is low, provided that

the recommended set-up and hold times are

observed. For clocked operation, shift/load must

be high. The two clock input perform identically;

one can be used as a clock inhibit by applying a

DIP

SOP

TSSOP

ORDER CODES

PACKAGE

TUBE

T&R

DIP

SOP

TSSOP

M74HCT165B1R

M74HCT165M1R M74HCT165RM13TR

M74HCT165TTR

high signal; to permit this operation clocking is

accomplished through a 2 input nor gate.

To avoid double clocking, however, the inhibit

signal should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

September 2001

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