ST24C08B1TR(2002) 데이터 시트보기 (PDF) - STMicroelectronics

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ST24C08B1TR
(Rev.:2002)

8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

STMicroelectronics 

Table 3. Device Select Code

Bit

b7

Device Select

1

Note: The MSB b7 is sent first.

Device Code

b6

b5

0

1

ST24/25C08, ST24/25W08

Chip

Enable

Block

Select

RW

b4

b3

b2

b1

b0

0

E

A9

A8

RW

Table 4. Operating Modes (1)

Mode

RW bit

MODE

Current Address Read

’1’

X

’0’

Random Address Read

X

’1’

Sequential Read

’1’

X

Byte Write

Multibyte Write (2)

’0’

X

’0’

VIH

Page Write

’0’

VIL

Notes: 1. X = VIH or VIL

2. Multibyte Write not available in ST24/25W08 versions.

Bytes

1

1

1 to 1024

1

8

16

Initial Sequence

START, Device Select, RW = ’1’

START, Device Select, RW = ’0’, Address,

reSTART, Device Select, RW = ’1’

Similar to Current or Random Mode

START, Device Select, RW = ’0’

START, Device Select, RW = ’0’

START, Device Select, RW = ’0’

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

Power On Reset: VCC lock out write protect. In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the VCC

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when VCC drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable VCC

must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS

Serial Clock (SCL). The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to VCC

to act as a pull up (see Figure 3).

Serial Data (SDA). The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to VCC to act as pull up (see Figure 3).

Chip Enable (E). This chip enable input is used to

set one least significant bit (b3) of the device select

byte code. This input may be driven dynamically or

tied to VCC or VSS to establish the device select

code.

Protect Enable (PRE). The PRE input pin, in ad-

dition to the status of the Block Address Pointer bit

(b2, location 3FFh as in Figure 7), sets the PRE

write protection active.

Mode (MODE). The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at VIL or VIH for the Byte Write

mode, VIH for Multibyte Write mode or VIL for Page

Write mode. When unconnected, the MODE input

is internally read as a VIH (Multibyte Write mode).

Write Control (WC). An hardware Write Control

(WC) feature is offered only for ST24W08 and

ST25W08 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycle. The Write Control sig-

nal is used to enable (WC = VIH) or disable (WC =

VIL) the internal write protection. When uncon-

nected, the WC input is internally read as VIL and

the memory area is not write protected.

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