ST24W08M1TR 데이터 시트보기 (PDF) - STMicroelectronics

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ST24W08M1TR

8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection

STMicroelectronics 

ST24/25C08, ST24/25W08

Table 7. AC Characteristics

(TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 3V to 5.5V or 2.5V to 5.5V)

Symbol

Alt

Parameter

Min

Max

Unit

tCH1CH2

tR

Clock Rise Time

1

µs

tCL1CL2

tF

Clock Fall Time

300

ns

tDH1DH2

tR

Input Rise Time

1

µs

tDL1DL1

tCHDX (1)

tF

tSU:STA

Input Fall Time

Clock High to Input Transition

300

ns

4.7

µs

tCHCL

tHIGH

Clock Pulse Width High

4

µs

tDLCL

tHD:STA

Input Low to Clock Low (START)

4

µs

tCLDX

tHD:DAT

Clock Low to Input Transition

0

µs

tCLCH

tLOW

Clock Pulse Width Low

4.7

µs

tDXCX

tSU:DAT

Input Transition to Clock Transition

250

ns

tCHDH

tSU:STO

Clock High to Input High (STOP)

4.7

µs

tDHDL

tCLQV (2)

tBUF

Input High to Input Low (Bus Free)

tAA

Clock Low to Next Data Out Valid

4.7

µs

0.3

3.5

µs

tCLQX

tDH

Data Out Hold Time

300

ns

fC

fSCL

Clock Frequency

100

kHz

tW (3)

tWR

Write Time

10

ms

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the

maximum programming time is doubled to 20ms.

Table 8. AC Measurement Conditions

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref.

Voltages

≤ 50ns

0.2VCC to 0.8VCC

0.3VCC to 0.7VCC

Figure 4. AC Testing Input Output Waveforms

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AI00825

DEVICE OPERATION (cont’d)

The 4 most significant bits of the device select code

are the device type identifier, corresponding to the

I2C bus definition. For these memories the 4 bits

are fixed as 1010b. The following bit identifies the

specific memory on the bus. It is matched to the

chip enable signal E. Thus up to 2 x 8K memories

can be connected on the same bus giving a mem-

ory capacity total of 16 Kbits. After a START condi-

tion any memory on the bus will identify the device

code and compare the following bit to its chip

enable input E.

The 6th and 7th bits sent, select the block number

(one block = 256 bytes). The 8th bit sent is the read

or write bit (RW), this bit is set to ’1’ for read and ’0’

for write operations. If a match is found, the corre-

sponding memory will acknowledge the identifica-

tion on the SDA bus during the 9th bit time.

6/16

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