CXD1175AM/AP
Points on the PCB Pattern Layout
1. Layout so that digital current does not flow to analog GND (part 1).
(See Component Side on page 19 for part 1.)
2. Capacitor C6 (between AVSS and AVDD) and capacitor C14 (between DVSS and DVDD) are important
factors to enhance the CXD1175A performance. Those capacitors should feature good high frequency
characteristics over 0.1µF (ceramic capacitor). Layout as close to the IC as possible.
3. Analog GND (AVSS) and Digital GND (DVSS) have a common voltage and a supply source. The DVSS of
A/D converter (part 2) location as close to the voltage source is possible will give even better results. That
is, a layout where the A/D converter is close to the voltage source is recommended. (See Component Side
on page 19 for part 2.)
4. AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13) are provided in the CXD1175A, and a common
voltage source should be used for them as for part 3. (See the paragraph for Latch Up Prevention.) (See
Soldering Side on page 19 for part 3.)
5. The A/D converter samples analog signals at the falling edge of clock. Accordingly, clocks fed to the A/D
converter should not be affected by jitter.
6. In this PCB, to evaluate A/D and D/A converters independently, an independent layout has been adopted
for the analog GND of A/D and D/A converters, from the voltage generation source. For the user’s actual
PCB even a common source poses no problems. For the CXA1106, as analog signals are output with the
supply voltage as reference, take care not to let noise interfere with the analog VDD of D/A converter.
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