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CXD2301Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXD2301Q Datasheet PDF : 23 Pages
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CXD2301Q
b) Digital clamp usage example (using self bias)
CLOCK IN
+4.75V
ACO4
0.1µ
0.1µ
+3.3V
0.1µ
VIDEO
IN1
VIDEO
IN2
24 23 22 21 20 19 18 17
0.1µ
25
16
26
15
0.1µ
27
14
28
13
75
29
12
30
0.1µ
11
31
10
32
9
12 3 4 56 78
Subtracter,
Comparator,
etc.
Clamp Level
Setting data
GND (analog)
GND (digital)
DAC,
PWM,
etc.
High impedance for all
information outside the
clamp interval
The relationship between the CCP voltage (Pin 32) variation and the ADIN voltage variation is
positive phase.
ADIN/VCCP = 3.0 (fs = 30MSPS)
– 10 –

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