Pin No. Symbol
29
ADIN
Equivalent circuit
AVDD
29
AVSS
CXD2301Q
Description
A/D converter block analog input.
30
OPO
32
CCP
AVDD
30
AVSS
AVDD
32
AVSS
Amplifier output.
The phase of this output is inverted
against the phase of VIN1, 2.
In standby mode, it becomes
high-impedance output condition.
Integrates the clamp control voltage.
The relationship between the CCP
voltage variation and the ADIN voltage
is positive phase.
• The following table shows the status of the digital output pins when the TEST pin is used with the CE and
SEL pins.
TEST CE SEL D1 D2 D3 D4 D5 D6 D7 D8
L
L
X D1 D2 D3 D4 D5 D6 D7 D8
L
H
X
LLLLLLLL
H
L
X
TEST mode
H
H
L
HLHLHLHL
H
H
H
LHLHLHLH
–5–