CXD2301Q 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD2301Q Datasheet PDF : 23 Pages
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Application Circuit
(1) When using the internal amplifier
a) Clamp usage example (using self bias)
CXD2301Q
CLOCK IN
ACO4
+3.3V
CK
CLAMP PULSE IN
Q
LATCH *
0.1µ
0.1µ
+4.75V
0.1µ
VREF
20k
24 23 22 21 20 19 18 17
0.1µ
25
16
D0
VIDEO IN
26
0.1µ
27
15
D1
14
D2
28
75
29
13
D3
12
D4
0.1µ
30
10p
31
11
D5
10
D6
32
9
D7
0.01µ
1 23 4 5 6 7 8
GND (analog)
GND (digital)
∗ Although the ADC sampling clock latches the clamp pulse, it is not needed for basic clamp
operation. However, depending on the relationship between the sampling frequency and the
clamp pulse frequency, a small beat might be generated as V sag. The latch circuit is valid at
this time.
–9–
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