MSM80C88A-10GS-K 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM80C88A-10GS-K

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C88A-10RS/GS/JS

EXTERNAL INTERFACE

Reset

CPU initialization is executed by the RESET pin. The MSM80C88A-10’s RESET High signal is

required for greater than 4 clock cycles.

The rising edge of RESET terminates the present operation immediately. The falling edge of

RESET triggers an internal reset sequence for approximately 10 clock cycles. After internal reset

sequence is finished, normal operation begins from absolute location FFFF0H.

Interrupt Operations

The interrupt operation is classified as software or hardware, and hardware interrupt is

classified as non-markable or maskable.

An interrupt causes a new program location which is defined by the interrupt pointer table,

according to the interrupt type. Absolute location 00000H through 003FFH is reserved for the

interrupt pointer table. The interrupt pointer table consists of 256-elements. Each element is 4

bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request

device during the interrupt acknowledge cycle.

Non-maskable Interrupt (NMI)

The MSM80C88A-10 has a non-maskable interrupt (NMI) which is of higher priority than a

maskable interrupt request (INTR).

An NMI request pulse width needs minimum of 2 clock cycles. The NMI will be serviced at the

end of the current instruction or between string manipulations.

Maskable Interrupt (INTR)

The MSM80C88A-10 provides another interrupt request (INTR) which can be masked by

software. INTR is level triggerd, so it must be held until interrupt request is acknowledged.

The INTR will be serviced at the end of the current instruction or between string manipulations.

Interrupt Acknowledge

During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt

enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto

the stack. During an acknowledge sequence, the CPU emits the lock signal from T2 of first bus

cycle to T2 of second bus cycle. At the second bus cycle, a byte is fetched from the external device

as a vector which identifies the type of interrupt. This vector is multiplied by four and used as

an interrupt pointer address (INTR only).

The interrupt Return (IRET) instruction includes a Flag pop operation which returns the

original interrupt enable bit when it restores the Flag.

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