PCA9521DP 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9521DP

Fast dual bidirectional bus buffer

NXP Semiconductors. 

NXP Semiconductors

PCA9521

Fast dual bidirectional bus buffer

10. Application information

10.1 Design considerations

Figure 10 shows the PCA9521 level shifting signals from 1.8 V to 3.3 V at 1 MHz clock

speed. The PCA9521 has excellent application to extending loads and providing

interfaces to connectors on high-speed microprocessor cards, well in excess of the

Fast-mode 400 kHz I2C-bus specification. Rise times are determined simply by the side of

the buffer with the slowest RC time constant.

4.5

voltage

(V)

3.5

002aaf287

(1)

2.5

(2)

1.5

0.5

−0.5

horizontal scale = 200 ns/div

time (ns)

(1) Input 33 pF

(2) Output 120 pF

Fig 10. 1.8 V to 3.3 V level shifting at 1 MHz

Figure 11 shows a typical application for the PCA9521. The IC can level shift between

different bus voltages without the need for external components. Higher bus voltages and

currents outside the range of the Standard-mode I2C-bus specification can be catered for,

providing a longer range capability and higher noise immunity.

The enable pin (EN) can be used to interface buses of different operating frequencies.

When certain bus sections are enabled, the system frequency may be limited by a bus

section having a slave device specified only to 100 kHz. When that bus section is

disabled, the slow slave is isolated and the remaining bus can be run at 400 kHz. The

timing performance and current sinking capability will allow the PCA9521 to run well in

excess of the 400 kHz maximum limit of the Fast-mode I2C-bus.

PCA9521

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 19 March 2013

© NXP B.V. 2013. All rights reserved.

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