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PCA9522

Fast dual bidirectional bus buffer with hot insertion logic

NXP Semiconductors. 

NXP Semiconductors

PCA9522

Fast dual bidirectional bus buffer with hot insertion logic

7. Functional description

Refer to Figure 1 “Block diagram of PCA9522”.

7.1 VCC, GND — supply pins

The PCA9522 can be driven from voltage supplies ranging from 2.7 V to 5.5 V. The

threshold level below which the output will begin to match the input is 33 % of VCC. Hence,

the operating voltage should be chosen with the required bus voltage, switching threshold,

and noise margins in mind.

7.2 SCLB, SCLC, SDAB, SDAC — buffer inputs/outputs

The two open-collector buffers (SCL and SDA) are identical and symmetrical. The buffers

can be driven from either direction, with the same buffering response. However, the hot

insertion logic is determined from the ‘backplane’ (SxxB) sides of the buffers. When the

one side (e.g., SxxB) of the buffer is being driven LOW (<0.3VCC) by another device on

the bus, the other side (e.g., SxxC) will be driven LOW by the IC to provide the buffered

output.

The ‘control’ or ‘input’ side is determined by the lowest externally driven signal. Therefore

if the ‘input’ is externally pulled to VSxxB = 250 mV, and the ‘output’ is externally pulled to

VSxxC = 500 mV, the buffer will pull the ‘output’ down further such that it becomes

VSxxC = VSxxB + Voffset. Should the ‘output’ subsequently become lower than the ‘input’ by

means of an external device pulling it LOW (VSxxC < VSxxB), control of the buffering

operation will switch sides. The voltage at the ‘input’ will then become

VSxxB = VSxxC + Voffset. Many bus buffers are prone to causing glitches during control

transition, but the PCA9522 shows negligible glitching even under the worst operating

conditions.

7.3 Enable (EN) — activate buffer operations

The enable input (EN) is used to disable the buffer, for the purpose of isolating sections of

the bus. The IC should only be disabled when the bus is idle, to prevent truncation of

commands which may confuse other devices on the bus.

Upon receiving a valid enable (EN) signal, the IC will wait to detect either a bus STOP

condition, or an IDLE condition as described in the I2C-bus [Ref. 1] and SMBus [Ref. 2]

specifications. This ensures that truncated transmissions are not communicated along the

newly enabled bus segment.

Enable may be used to progressively activate sections of the bus during system start-up.

Bus sections slow to respond on power-up can be kept isolated from the main system to

avoid interference and collisions.

The EN pin may be pulled up higher than the VCC of the buffer, further enhancing the

capability of the PCA9522 in a level shifting role. For example, a microprocessor could

drive EN, SCLB and SDAB at 5 V, while the buffer VCC, SCLC and SDAC ports are at

3.3 V.

Similarly, the threshold level of the EN pin allows a 1.8 V device to enable an PCA9522

with a VCC of 3.3 V.

PCA9522

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 28 September 2011

© NXP B.V. 2011. All rights reserved.

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