PCA9525DP 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9525DP

Simple 2-wire bus buffer

NXP Semiconductors. 

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

10. Application information

10.1 Design considerations

Figure 13 shows a typical data transfer through the PCA9525. The PCA9525 has

excellent application to extending loads and providing interfaces to connectors on high

speed microprocessor cards. PCA9525 can operate well in excess of the Fast-mode

400 kHz I2C-bus specification (Ref. 1). Rise times are determined simply by the side of

the buffer with the slowest RC time constant.

SCL

(clock)

SDA

(data)

A0

A1

A2

A3

A4

A5

A6

W

(master) (master) (master) (master) (master) (master) (master) (master)

ACK

(slave)

S

START

sequence

purpose of bit (address bit 5)

device asserting data line (master/slave)

master side of PCA9525/PCA9605

slave side of PCA9525/PCA9605

SDA direction

'hand over' pulses upon change

of device asserting the data line

Remark: Input to output delay exaggerated for clarity.

Fig 13. Typical communication sequence through the PCA9525

P

STOP

sequence

002aaf341

Figure 14 shows a typical application for the PCA9525. In most applications there will be a

single master on the Sxx_IN side of the buffer. One or more PCA9525s can be connected

to this master, giving multiple isolated bus sections on which the slaves are located. Each

bus section can have the maximum permissible load capacitance, and this capacitance

will not influence any other bus section.

The master can control the enable (EN) signals such that each bus section can be

independently activated. This allows for slaves sharing the same address to be placed on

different bus sections and thus uniquely addressed.

The enable pin (EN) can similarly be used to interface buses of different operating

frequencies. When certain bus sections are enabled, the system frequency may be limited

by a bus section having a slave device specified only to 400 kHz (Fast-mode). When that

bus section is disabled, the slow slave is isolated and the remaining bus can be run at

1 MHz (Fast-mode Plus).

PCA9525

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 25 February 2011

© NXP B.V. 2011. All rights reserved.

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