PCA9525DP 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9525DP

Simple 2-wire bus buffer

NXP Semiconductors. 

NXP Semiconductors

PCA9525

Simple 2-wire bus buffer

Figure 11 shows that by choosing an appropriate value of pull-up resistance (or adding

additional load capacitance if that is preferred), the rate of rise of both input and output

can be matched, and the glitch on the rising edge eliminated.

Fig 11. Matched ‘input’ and ‘output’ rise times

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9.2 Operating conditions

A full byte transaction is shown in Figure 12. SDA_IN and SDA_OUT are shown at the top

of the image, and SCL_IN and SCL_OUT are shown at the bottom. The START condition,

address bits, read/write bit, acknowledge bit and STOP condition can all be clearly seen.

Fig 12. Full 400 kHz I2C-bus address byte transaction

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PCA9525

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 25 February 2011

© NXP B.V. 2011. All rights reserved.

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