PCD5043 데이터 시트보기 (PDF) - Philips Electronics
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PCD5043 Datasheet PDF : 24 Pages
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Philips Semiconductors
DECT burst mode controller
4 BLOCK DIAGRAM
Objective specification
PCD5043
handbook, full pagewidth
to CODEC/
Highway
3-wire synthesizer
interface
Rx/Tx data
8051/68000
interface
PCD5043
DECT
BURST MODE
CONTROLLER
TIMING, CONTROL,
CLOCK
GENERATION
SPEECH
INTERFACE
internal
bus
DATA MEMORY
2 kbyte RAM
RF INTERFACE
PROGRAMMABLE
COMMUNICATION
CONTROLLER (PCC)
MICROCONTROLLER
INTERFACE
PCC
PROGRAM MEMORY
4 kbyte ROM
Fig.1 Block diagram.
MBH742
5 PINNING (see Fig.2)
SYMBOL
AD0 to AD7
ALE
CS
A8 to A10
VDD1
PROC_CLK
PIN
1 to 8
9
10
13 to 11
14
15
VSS1
16
XTAL1
17
XTAL2
18
VSS2
19
RESET_OUT
20
RD
21
WR
22
RDY
23
INT
24
CLK100
25
1996 Oct 31
TYPE(1)
I/O
I
I
I
P
O
P
I
O
P
O
I
I
O
O
O
DESCRIPTION
address/Data bus
address latch enable
chip select (active LOW)
address bus
positive supply 1
microcontroller clock; programmable from fCLK/64 to fCLK, where fCLK
is the crystal oscillator frequency
negative supply 1
crystal oscillator input
crystal oscillator output
negative supply
watchdog timer output; intended to reset the external microcontroller
when expired
read (active LOW)
write (active LOW)
ready signal (active LOW), to initiate wait states in the
microcontroller (open drain)
interrupt (active LOW)
100 Hz frame timer
4
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