PCF2113 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCF2113

LCD controllers/drivers

NXP Semiconductors. 

NXP Semiconductors

PCF2113x

LCD controllers/drivers

9.2 Return home

‘Return home’ sets the DDRAM address counter to 0 and returns the display to its original

position if it was shifted. DDRAM contents do not change. The cursor or blink position

goes to the left of the first display line. I/D and S of entry mode do not change.

9.3 Entry mode set

9.3.1 Bit I/D

When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when

data is written into or read from the DDRAM or CGRAM. The cursor or blink position

moves to the right when incremented and to the left when decremented. The cursor

underline and cursor character blink are inhibited when the CGRAM is accessed.

9.3.2 Bit S

When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1)

during a DDRAM write. Thus it appears as if the cursor stands still and the display moves.

The display does not shift when reading from the DDRAM, or when writing to or reading

from the CGRAM.

When S = 0, the display does not shift.

9.4 Display control (and partial Power-down mode)

9.4.1 Bit D

The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not

affected and can be displayed immediately by setting D = 1.

When the display is off (D = 0) the chip is in partial Power-down mode:

• The LCD outputs are connected to VSS

• The LCD generator and bias generator are turned off

Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all

outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running

during partial Power-down mode (‘display off’) the chip can still execute instructions. Even

lower current consumption is obtained by inhibiting the oscillator (pin OSC = VSS).

To ensure IDD < 1 µA, pin PD and the parallel bus pins DB7 to DB0 should be connected

to VDD, pins RS and R/W to VDD or left open-circuit.

Recovery from Power-down mode: connect pin PD back to VSS, if necessary pin OSC

back to VDD and send a ‘display control’ instruction with D = 1.

9.4.2 Bit C

The cursor is displayed when C = 1 and inhibited when C = 0. The cursor is displayed

using 5 dots in the 8th line (see Figure 12). Even if the cursor disappears, the display

functions like I/D, remain in operation during display data write.

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

© NXP B.V. 2008. All rights reserved.

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