PCF2119AU 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCF2119AU

LCD controller/drivers

NXP Semiconductors. 

NXP Semiconductors

PCF2119x

LCD controllers/drivers

7.2 Pin description

Table 3.

Symbol

VDD1

VDD2

VDD3

E

Pin description

Pin

1 to 6

7 to 14

15 to 18

19

T1 and T2 20 and 21

VSS1

22 to 29

VSS2

30 to 35

VLCDSENSE

36

VLCDOUT

37 to 43

VLCDIN

44 to 49

dummy

R8 to R1,

R17,

R17DUP,

R18,

R9 to R16

C80 to C41,

C40 to C1

dummy

SCL

T3

50

51 to 58,

59,

100

141,

142 to 149

60 to 99,

101 to 140

150

151 and 152

153

POR

154

Description

supply voltage 1 (logic)

[1] supply voltage 2 (for high voltage generator)

[1] supply voltage 3 (for high voltage generator)

[2] data bus clock input

• set HIGH to signal the start of a read or write operation

• data is clocked in or out of the chip on the negative edge

of the clock

test pins

• must be connected to VSS1

[3] ground supply voltage 1

• for all circuits, except of high voltage generator

[3] ground supply voltage 2

• for high voltage generator

input for voltage multiplier regulation circuitry and for the bias

level generation

• if VLCD is generated internally then this pin must be

connected to VLCDOUT and VLCDIN

• if VLCD is generated externally then this pin must be

connected to VLCDIN only

VLCD output

• if VLCD is generated internally then this pin must be

connected to VLCDIN and to VLCDSENSE

• if VLCD is generated externally then this pin must be left

open-circuit

input for LCD bias level generator

• if VLCD is generated internally then this pin must be

connected to VLCDOUT and to VLCDSENSE

• if VLCD is generated externally then this pin must be

connected to VLCDSENSE and to the external VLCD power

supply

[4] -

LCD row driver output

• R17 has two pins: R17 and R17DUP

• R17 and R18 drive the icons

LCD column driver output

[4] -

[5] I2C-bus serial clock input

test pin

• open-circuit

• not user accessible

external Power-On Reset (POR) input

PCF2119X

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 9 — 14 April 2011

© NXP B.V. 2011. All rights reserved.

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