PCF8801 데이터 시트보기 (PDF) - Philips Electronics
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PCF8801 Datasheet PDF : 20 Pages
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Philips Semiconductors
LCD driver for 140 × 2 segments
Product specification
PCF8801
Table 3 Output multiplexer truth table
n = 1 to 140; X = don’t care.
CONTROL INPUT
DATA INPUT
COMMON M
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
IOn_1
0
1
X
X
0
1
X
X
IOn_2
X
X
0
1
X
X
0
1
DATA
OUTPUT
OMn
0
1
0
1
1
0
1
0
The backplane drivers generate two output signals called
COM1 and COM2 which connect directly to LCD
backplane 1 and to backplane 2 respectively.
These signals have 3 voltage levels called VDD, VMID and
VSS, where VSS = 0 V and VMID = 1⁄2VDD. VMID is the LCD
bias voltage generated by the LCD bias generator.
Figure 2 is a timing diagram for the output multiplexer,
frame generator and backplane drivers.
Routing block and output drivers
The layout of the LCD interconnection requires each of the
140 outputs (OM1 to OM140) from the output multiplexer
to be mapped to the corresponding pixel in each LCD
character by the routing block. The outputs of the routing
block are fed to output drivers whose outputs are
pads S1 to S140. Table 4 shows which pixel is driven by
which data bit output by the shift register for the first LCD
character. There are 7 characters in total, each character
has 40 data points, so routing is performed on a
point-by-point basis.
A pixel has 2 segments which are activated by backplane
drive signals COM1 and COM2 respectively. If DIR = 0,
the first data bit of the data stream to be loaded into the
shift register is routed to the first pixel. Data bit SH1_1 is
routed to pixel 1, activated by COM1, and data bit SH1_2
is routed to pixel 1, activated by COM2.
handbook, full pagewidth
RESET
OSC
COMMON
M
COM1
COM2
OMn
(n = 1 to 140)
IOn_1 IOn_2 IOn_1 IOn_2 IOn_1 IOn_2 IOn_1 IOn_2 IOn_1
t
MGL916
Fig.2 Timing diagram for output multiplexer, frame generator and backplane drivers.
2000 Feb 04
6
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