PCF8593T 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCF8593T

Real-time clock/calendar

NXP Semiconductors. 

NXP Semiconductors

PCF8593

Low power clock and calendar

7.3 Control and status register

The control and status register is defined as the memory location 00h with free access for

reading and writing via the I2C-bus. All functions and options are controlled by the

contents of the control and status register (see Figure 4).

MSB

7

6

5

4

3

2

013aaa382

Fig 4. Control and status register

LSB

memory location 00h

1

0

timer flag: 50 % duty factor

seconds flag if alarm enable bit

is logic 0

alarm flag: 50 % duty factor

minutes flag if alarm enable bit

is logic 0

alarm enable bit:

logic 0:

alarm disabled: flags toggle

alarm control register to disabled

(memory locations 08h to 0Fh

are free RAM space)

logic 1:

enable alarm control register

(memory location 08h is the

alarm control register)

mask flag:

logic 0:

logic 1:

read locations 05h to 06h

unmasked

read date and month count

directly

function mode:

00

clock mode 32.768 kHz

01

clock mode 50 Hz

10

event-counter mode

11

test modes

hold last count flag:

logic 0: count

logic 1: store and hold last count in

capture latches

stop counting flag:

logic 0: count pulses

logic 1: stop counting, reset divider

PCF8593

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 04 — 6 October 2010

© NXP B.V. 2010. All rights reserved.

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