PE4268 데이터 시트보기 (PDF) - Peregrine Semiconductor Corp.
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PE4268 Datasheet PDF : 11 Pages
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PE4268
Product Specification
Figure 3. Pin Configuration (Top View)
TX1 1
GND 2
TX2 3
GND 4
GND 5
20-lead QFN
4x4mm
Exposed Solder Pad
15 RX1
14 RX2
13 GND
12 RX3
11 RX4
Table 2. Pin Descriptions
Pin No.
11
2
31
4
5
6
7
8
9
10
111
121
13
141
151
16
17
18
191
20
Pin Name
TX1
GND
TX2
GND
GND
VDD
V3
V2
V1
GND
RX4
RX3
GND
RX2
RX1
GND
GND
GND
ANT
GND
Description
RF I/O - TX1
Ground
RF I/O – TX2
Ground
Ground
Supply
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Switch control input, CMOS logic level
Ground
RF I/O - RX4
RF I/O - RX3
Ground
RF I/O - RX2
RF I/O - RX1
Ground
Ground
Ground
RF Common – Antenna Input
Ground
Note 1: Blocking capacitors needed only when connected to an
external non-zero DC voltage.
Table 3. DC Electrical Specifications
Parameter
Min
Typ
Max
Units
VDD Supply Voltage
2.4
2.6
2.8
V
IDD Power Supply Current
(VDD = 2.6V)
13
20
µA
Control Voltage High
0.7 x VDD
V
Control Voltage Low
0.3 x VDD
V
Document No. 70-0165-03 │ www.psemi.com
Table 4. Absolute Maximum Ratings
Symbol
VDD
VI
Parameter/Conditions
Power supply voltage
Voltage on any input
Min Max Units
-0.3 4.0
V
-0.3
VDD+
0.3
V
TST
Storage temperature range
-65 +150 °C
TOP
Operating temperature range -40 +85
°C
TX input power (50 Ω)
PIN
RX input power (50 Ω)
+38
dBm
+23
VESD1
ESD Voltage (HBM,
MIL_STD 883 Method
3015.7)
ESD Voltage (MM, JEDEC,
JESD22-A114-B)
ESD Voltage (CDM, JEDEC,
JESD22-C101-A)
1500 V
100
V
2000 V
Note 1: ANT port rated higher per applications section, see page 4.
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Truth Table
Path
ANT – RX1
ANT – RX2
ANT – RX3
ANT – RX4
ANT - TX1
ANT - TX2
V3
V2
V1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
x
1
1
x
©2005 Peregrine Semiconductor Corp. All rights reserved.
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