DAC-8841FP 데이터 시트보기 (PDF) - Analog Devices
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DAC-8841FP Datasheet PDF : 11 Pages
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DAC-8841
CIRCUIT OPERATION
During system power up a logic low on the preset PR pin forces
The DAC-8841 is a general purpose multiple-channel ac or do
all DAC registers to 80^ which in turn forces all the buffer am
signal level adjustment device designed to replace potentiometers plifier outputs to equal half-scale. The transfer equation (1)
used in the three-terminal connection mode. Eight independent
shows that in the preset condition (80h) that Vqut will equal
channels of programmable signal level control are available in
ViN. The asynchronous PR input pin can be activated at any
this 24-pin package device. The outputs are completely buffered time to force the DAC registers to the half-scale code 80h. This
providing up to 5 mA of drive current to drive external loads.
is generally the most convenient place to start for general pur
The DAG and amplifier combination shown in Figure 18 pro
pose adjustment applications.
duces two-quadrant multiplication of the signal inputs applied to
ViN times the digital input control word. In addition the DAC-
8841 provides a 1 MHz gain-bandwidth product in the two-
ADJUSTING AC OR DC SIGNAL LEVELS
The two-quadrant multiplication operation of the DAC-8841 is
quadnmt multiplying channel. Operating from a 5 V power
shown in Figiure 18. For dc operation the equation describing
supply, analog inputs to +1.5 V which generate outputs to
the relationship between Vjn, digital inputs and Vqut is:
+3 V are easily accommodated.
VouiiD) = (D/128) X (V/jv - VrefL) + Vref^ (1)
where D is a decimal number between 0 and 255.
The acmal output voltages generated with a fixed 1.5 V dc input
on VjN and VrefL = 0 V are summarized in this table.
E Vqut =2 XVdac when Vrepl =ov
:r2(D/256)xV,M
T = (D/128)xV,n
GENERALCASE WHENVrep L x OV:
VouT= (D/128)x (V|n- Vref L) + Vrhf L
E DAC8841 INPUT-OUTPUT VOLTAGE RANGE
VpD = tSV
Vref' .=ov
L n - FF..
7 1 / .DsCOh
(I~— O X
O
CO
^ aD=40h
1
S DsOOh
0
2
4
V,N-Volts
Vqut= 2 XV,n (D/256). where D=0 TO255
B Figure 18. DAC Plus Amplifier Combine to Produce Two-
Quadrant Multiplication
In order to be easy to use with a controlling microprocessor, a
O simplelayout-efficient three-wire serial data interface wascho
Decimal Input (D)
0
1
2
127
128
129
254
255
Vout(®)
0.000 V*
0.012*
0.024*
1.488
1.500
1.512
2.976
2.988
Comments
(ViN = 1.5 V, VrefL = 0 V)
Zero Scale
Half Scale = Vin
Full Scale
(FS) « 2 X ViN
*See "Operation Near Ground."
Notice that the output polarity is the same as the input polarity
when the DAC register is loaded with 255 (in binary = all
ones). Also note that the output does not exactly equal two
times the input voltage. This is a result of the R-2R ladder DAC
chosen. When the DAC register is loaded with 0, the output is
VrefL. The acmal voltage measured when setting up a DAC in
this example will vary within the ± 1 LSB linearity error specifi
cation of the DAC-8841. The actual voltage error would be
±0.012 V.
Operation Near ground - The input stage of the internal buffer
amplifier functions down to groimd, but the output stage cannot
pull lower than the internal ground voltage. When a DAC out
put tries to output a voltage at or below the internal ground po
sen. This interface can be easily adapted to almost all microcom tential, it saturates and appears like a 50 fl resistor to ground.
puter and microprocessor systems. A clock (CLK), serial data
The typical saturation voltage appearing at the output is 20 mV,
input (SDI) and a load(LD) strobe pin make up the three-wire see Figure 9. The 100 mV worst case zero-scale voltage specifi
interface. The 12-bitinput data word used to change the value
cation reflects this saturation effect, including the worst case
of the internal DAC registerscontains a 4-bit address and 8-bits anticipated variationof the internal ground resistances, quies
of data. Using this combination, any DAC registercan be
cent currents and buffer sinking current. Linearity is measured
changed without disturbing the other devices. A serialdata out
betweencode 8io and code 255^0 to avoid this samration effect.
put (SDO) pin simplifies cascading multiple DAC-8841s without In summary, the transfer function of each DAC will be a
adding address decoder chips to the system.
straight line from code 8 to code 255 when VrefL = 0 V. For
input codes 0 to 7, some DAC outputs will be satiurated in the
zero-scale output voltage region; therefore, changing digjtal code
0 to 1 may not change the output voltage when VrefL - 0 V.
-8-
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