HT48C06 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT48C06

Cost-Effective I/O Type 8-Bit MCU

Holtek Semiconductor 

HT48R05A-1/HT48C05/HT48R06A-1/HT48C06

WS2

0

0

0

0

1

1

1

1

WS1 WS0

Division Ratio

0

0

1:1

0

1

1:2

1

0

1:4

1

1

1:8

0

0

1:16

0

1

1:32

1

0

1

1

1:64

1:128

WDTS Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a ²warm reset², and

only the PC and SP are reset to zero. To clear the con-

tents of WDT (including the WDT prescaler), three

methods are adopted; external reset (a low level to

RES), software instruction and a ²HALT² instruction.

The software instruction include ²CLR WDT² and the

other set - ²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one can be active depend-

ing on the option - ²CLR WDT times selection option². If

the ²CLR WDT² is selected (i.e. CLRWDT times equal

one), any execution of the ²CLR WDT² instruction will

clear the WDT. In the case that ²CLR WDT1² and ²CLR

WDT2² are chosen (i.e. CLRWDT times equal two),

these two instructions must be executed to clear the

WDT; otherwise, the WDT may reset the chip as a result

of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following...

· The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

· The contents of the on chip RAM and registers remain

unchanged.

· WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

· AlloftheI/Oportsmaintaintheiroriginalstatus.

· The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the ²CLR WDT² instruction and is set when execut-

ing the ²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the PC and SP; the others keep their original status.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by the options. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it is awakening from an interrupt, two

sequences may happen. If the related interrupt is dis-

abled or the interrupt is enabled but the stack is full, the

program will resume execution at the next instruction. If

the interrupt is enabled and the stack is not full, the regu-

lar interrupt response takes place. If an interrupt request

flag is set to ²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

Once a wake-up event occurs, it takes 1024 tSYS (sys-

tem clock period) to resume normal operation. In other

words, a dummy period will be inserted after wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

There are three ways in which a reset can occur:

· RES reset during normal operation

· RES reset during HALT

· WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the PC and SP, leaving the other cir-

cuits in their original state. Some registers remain un-

changed during other reset conditions. Most registers

are reset to the ²initial condition² when the reset condi-

tions are met. By examining the PDF and TO flags, the

program can distinguish between different ²chip resets².

TO PDF

RESET Conditions

0 0 RES reset during power-up

u u RES reset during normal operation

0 1 RES wake-up HALT

1 u WDT time-out during normal operation

1 1 WDT wake-up HALT

Note: ²u² means ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

Rev. 1.10

11

June 9, 2004

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