PEB20324 데이터 시트보기 (PDF) - Infineon Technologies

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PEB20324

Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X

Infineon Technologies 

PEB 20324

PEF 20324

Pin Descriptions

Table 2-4

Pin No.

89

85

86

81

83

82

84

Pin Descriptions by Functional Block: Port 3 Serial Interface

Symbol Type Description

RxCLK3 I

Receive Clock 3

The clock input pin used for sampling the data on

RxD3. The MUNICH128X supports the following PCM

clock rates, programmed via the MODE1 register:

T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;

E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.

RxD3

I

Receive Data 3

The data input pin which is sampled using RxCLK3.

RSP3

I

Receive Synchronization Pulse 3

The input pin used for Rx PCM frame synchronization;

the synchronization pulse marks the first bit in the

PCM frame.

TxCLK3 I

Transmit Clock 3

The clock input used for clocking out the data on

TxD3. In most applications, the signal that drives this

pin is externally connected to RxCLK3.

TxD3

O Transmit Data 3

Provides the data which is clocked out of the

MUNICH128X by TxCLK3; data is push-pull for active

bits in the PCM frame and TRISTATE™ for inactive

bits.

TSP3

I

Transmit Synchronization Pulse 3

The input pin used for Tx PCM frame synchronization;

the synch. pulse marks the last bit in the PCM frame.

TxDEN3 O

Transmit Data Enable 3

An active low output signal which specifies data on the

TxD3 output pin is valid.

Hardware Reference Manual

20

04.99

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