PI6C105H 데이터 시트보기 (PDF) - Pericom Semiconductor
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PI6C105H Datasheet PDF : 15 Pages
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PI6C105
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Select Functions
SEL100/66# Function
0
66 MHz active
1
100 MHz active
Clock Enable Configuration
CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK [0:1] PCICLK [1:5] PCICLK_F Other Clocks Crystal
X
X
0
low
low
low
stopped
off
0
0
1
low
low
33 MHz
running
running
0
1
1
low
33 MHz
33 MHz
running
running
1
0
1
100/66 MHz
low
33 MHz
running
running
1
1
1
100/66 MHz
33 MHz
33 MHz
running
running
VCO's
off
running
running
running
running
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock
output and test mode enable.
The PI6C105 is a slave receiver device. It can not be read back.
Sub addressing is not supported. To change one of the control
bytes, all preceding bytes must be sent.
Every byte put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving device.
During normal data transfers, SDATA changes only when SCLK is
LOW. Exceptions: A HIGH-to-LOW transition on SDATA while
SCLK is HIGH indicates a start condition. A LOW-to-HIGH
transition on SDATA, while SCLK is HIGH, is a stop condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended
with a stop condition. The first byte after a start condition is always
a 7-bit address byte followed by a read/write bit. (HIGH = read
from addressed device, LOW= write to addressed device). If the
devices own address is detected, PI6C105 generates an acknowl-
edge by pulling SDATA line LOW during ninth clock pulse, then
accepts the following data bytes until another start or stop condi-
tion is detected.
Following acknowledgment of the address byte (D2), two more
bytes must be sent:
1. Command Code byte, and
2. Byte Count byte.
Although the data bits on these two bytes are dont care, they
must be sent and acknowledged.
PI6C105 I2C Address Assignment
A7 A6 A5 A4 A3 A2 A1 A0
1
1
0
1
0
0
1
0
250
PS8316 03/15/99
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