DMC73CE167 데이터 시트보기 (PDF) - Daewoo Semiconductor

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DMC73CE167

8Bit Single Chip Microcontroller

Daewoo Semiconductor 

22

8Bit Single Chip Microcontroller

DMC73C167

4.8 Interrupt and Reset Priorities

The DMC73C167 has priority servicing of five interrupt levels and RESET. These levels

are defined as shown in Table 4-3. The TRAP instructions branch to two-byte location in a

reserved section of memory called the TRAP vector table. As shown in Figure 4-5. each trap

location stores a 16-bit address that references either the reset function (TRAP0), one of the

five interrupt service routines (TRAP1-INT1, TRAP2-INT2, TRAP3-INT3, TRAP4-INT4, TRAP5-

INT5), or a subroutine (TRAP6-23). Once the interrupt has been acknowledged, the CPU then

pushes the contents of the status register and the program counter (MSB and LSB) onto the

stack and zeros the status register, including the global interrupt Enable (I) bit.

The CPU reads an interrupt code from the interrupt logic and branches to the address

contained in the corresponding interrupt vector location in memory. The interrupt service routine

can explicitly enable nested interrupts by executing the EINT instruction to directly set the I bit

in the status register to 1, thus permitting routine is completed, it returns to the previous interrupt

service routine by executing the RETI instruction.

Table 4-3. Interrupt and Reset Priorities

Level

0

1

2

3

4

5

Name

/Reset

INT1

INT2_0

INT2_1

INT3_0

INT3_1

INT4

INT5_0

INT5_1

INT5_2

Source

External

External

Timer 1

Timer 2

External

Timer 3

OSD

External

12C master

12C slave

Trigger Factor

Active Low

Falling/Rising

Timer 1 underflow

Timer 2 underflow

Falling/Rising

Timer3 underflow

OSD enable

Falling/Rising

Data ready from slave

Slace address selected

Vector

MSB LSB

FFFEh FFFFh

FFFCh FFFDh

FFFAh FFFBh

FFF8h FFF9h

FFF6h FFF7h

FFF4h FFF5h

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