DMC73CE167 데이터 시트보기 (PDF) - Daewoo Semiconductor

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DMC73CE167

8Bit Single Chip Microcontroller

Daewoo Semiconductor 

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8Bit Single Chip Microcontroller

DMC73C167

Table 5-9. P12 010Ch DDATA D Port Data

Bit

7

6

5

4

3

2

1

0

R

W

-

-

-

-

DDATA3 DDATA2 DDATA1 DDATA0

Table 5-10. D Port Control Register Operation

DDDRn

0

1

Driection

Input Port

Output Port

DDATAn(Read)

0 ; Input 'Low'

1 : Input 'High'

Written Data

DDATAn(Write)

Invalid

0 ; Output 'Low'

1 : Output 'High'

5.2 Device Initialization

Interrupt level 0 (RESET) cannot be masked and will be recognized immediately, even in the

middle of an instruction. To execute the level-0 interrupt, the RESET pin must be held low

for a minimum of five internal clock cycles to guarantee recognition by the device. During

assertion of the RESET pin, the following operations are performed prior to the first

instruction acquisition.

1) All zeros are written to the status register. This disables all interrupts and clears all interrupt

flags.

2) The initialized data is written to the peripheral register.

3) The MSB and LSB values of the program counter just before RESET are stored in the R0

and R1 (A and B) registers, respectively.

4) The stack pointer is initialized to 01h.

5) The MSB and LSB of the reset vector are fetched from locations FFFEh and FFFFh,

respectively (see Table 4-5), and located into the program counter.

5.3 I/O Control Registers

The I/O control registers are lcated in the peripheral file and are responsible for interrupt

control. The DMC73C167 contains the I/O Control 0 (IOCTL0), I/O Control 1 (IOCTL1),

I/O Control 2 (IOCTL2), I/O Control 3 (IOCTL3), and I/O Control 4 (IOCTL4) registers, the

I/O Control registers are mapped into lcations P0 (IOCTL0), P1 (IOCTL1), P2 (IOCTL2), P3

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