PIC12F617 데이터 시트보기 (PDF) - Microchip Technology
부품명
상세내역
제조사
PIC12F617 Datasheet PDF : 212 Pages
| |||
PIC12F609/615/617/12HV609/615
2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F609/615/12HV609/615
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
On-chip Program
Memory
Wraps to 0000h-03FFh
0004h
0005h
03FFh
0400h
1FFFh
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
PC<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
On-Chip
Program
Memory
Interrupt Vector
Page 0
Wraps to 0000h-07FFh
0004h
0005h
07FFh
0800h
1FFFh
2.2 Data Memory Organization
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. The RP0 bit of the STATUS register is the
bank select bit.
RP0
0 Bank 0 is selected
1 Bank 1 is selected
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
2010 Microchip Technology Inc.
DS41302D-page 11
Share Link: 