AD9708-EB 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

AD9708-EB

8-Bit, 100 MSPS+ TxDAC® D/A Converter

Analog Devices 

AD9708

OPTIONAL

EXTERNAL

REF BUFFER

ADDITIONAL

LOAD

0.1␮F

2k⍀

REFLO

+1.2V REF

REFIO

FS ADJ

AD9708

+5V

0.1␮F

COMP1 AVDD

50pF

CURRENT

SOURCE

ARRAY

Figure 13. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 14. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input

impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

AVDD

0.1␮F

AVDD

EXTERNAL

REF

VREFIO

REFLO

+1.2V REF

REFIO

FS ADJ

RSET IREF =

VREFIO/RSET

AD9708

COMP1 AVDD

50pF

CURRENT

SOURCE

ARRAY

REFERENCE

CONTROL

AMPLIFIER

Figure 14. External Reference Configuration

The AD9708 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, IOUTFS.

The control amplifier is configured as a V-I converter, as shown

in Figure 14, such that its current output, IREF, is determined by

the ratio of the VREFIO and an external resistor, RSET, as stated

in Equation 4. The control amplifier allows a wide (10:1)

adjustment span of IOUTFS over a 2 mA to 20 mA range by setting

IREF between 62.5 µA and 625 µA. The wide adjustment span of

IOUTFS provides several application benefits. The first benefit

relates directly to the power dissipation of the AD9708, which is

proportional to IOUTFS (refer to the POWER DISSIPATION

section). The second benefit relates to the 20 dB adjustment,

which is useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 1.8 MHz and can be reduced by connecting an

external capacitor between COMP1 and AVDD. The output of

the control amplifier, COMP1, is internally compensated via a

50 pF capacitor that limits the control amplifier small-signal

bandwidth and reduces its output impedance. Any additional

external capacitance further limits the bandwidth and acts as

a filter to reduce the noise contribution from the reference

amplifier. If IREF is fixed for an application, a 0.1 µF ceramic chip

capacitor is recommended.

IREF can be varied for a fixed RSET by disabling the internal

reference and varying the common-mode voltage over its

compliance range of 1.25 V to 0.10 V. REFIO can be driven by

a single-supply amplifier or DAC, thus allowing IREF to be var-

ied for a fixed RSET. Since the input impedance of REFIO is

approximately 1 MΩ, a simple R-2R ladder DAC configured in

the voltage mode topology may be used to control the gain. This

circuit is shown in Figure 15 using the AD7524 and an external

1.2 V reference, the AD1580. Note another AD9708 could also

be used as the gain control DAC since it can also provide a

programmable unipolar output up to 1.2 V.

ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS

The AD9708 produces two complementary current outputs,

IOUTA and IOUTB, which may be converted into complementary

single-ended voltage outputs, VOUTA and VOUTB, via a load resistor,

RLOAD, as described in the DAC TRANSFER FUNCTION

section. Figure 16 shows the AD9708 configured to provide a

positive unipolar output range of approximately 0 V to +0.5 V

for a double terminated 50 Ω cable for a nominal full-scale

current, IOUTFS, of 20 mA. In this case, RLOAD represents the

equivalent load resistance seen by IOUTA or IOUTB and is

equal to 25 Ω. The unused output (IOUTA or IOUTB) can be

connected to ACOM directly or via a matching RLOAD. Different

values of IOUTFS and RLOAD can be selected as long as the posi-

tive compliance range is adhered to.

AD9708

IOUTFS = 20mA

IOUTA 22

IOUTB 21

50⍀

25⍀

VOUTA = 0 TO +0.5V

50⍀

Figure 16. 0 V to +0.5 V Unbuffered Voltage Output

Alternatively, an amplifier could be configured as an I-V converter

thus converting IOUTA or IOUTB into a negative unipolar

AVDD

AVDD

1.2V

AD1580

OPTIONAL

BANDLIMITING

CAPACITOR

REFLO

COMP1 AVDD

RFB

VDD

OUT1

AD7524

OUT2

VREF

AGND

DB7–DB0

0.1V TO 1.2V

+1.2V REF

REFIO

FS ADJ

RSET IREF =

VREF/RSET

AD9708

50pF

CURRENT

SOURCE

ARRAY

Figure 15. Single-Supply Gain Control Circuit

–8–

REV. B

Share Link: