HI3246JCQ 데이터 시트보기 (PDF) - Intersil
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HI3246JCQ Datasheet PDF : 16 Pages
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HI3246
Test Circuits (Continued)
SIGNAL
SOURCE
VIN
fC
4
-1kHz
2VP-P SINE WAVE
SIGNAL
SOURCE
fC
HI3246
8
CLK
CLK
LATCH
A
COMPARATOR
B
A>B
+
LATCH
1/8
16 LSB
FIGURE 6. ERROR RATE MEASUREMENT CIRCUIT
PULSE
COUNTER
100MHz
OSC1
φ: VARIABLE
AMP
VIN
fR
CLK
OSC2
100MHz
PECL
BUFFER
HI3246
8
LOGIC
ANALYZER
1024
SAMPLES
FIGURE 7. SAMPLING DELAY/APERTURE JITTER
MEASUREMENT CIRCUIT
VRT
VIN
VRM2
VRB
CLK
∆υ
∆t
VIN
CLK
129
128
127
σ (LSB)
126
125
SAMPLING TIMING FLUCTUATION
(= APERTURE JITTER)
NOTE: Where σ (LSB) is the deviation of the output codes when the
largest slew rate point is sampled at the clock which has exactly the
same frequency as the analog input signal, the aperture jitter tAJ is:
tAJ
=
σ
/ ∆-∆----υ-t-
=
σ
/
2----52---6--
x
2πf .
FIGURE 8. APERTURE JITTER MEASUREMENT METHOD
Operating Modes
The HI3246 has two types of operating modes which are selected with Pin 45 (SELECT).
TABLE 2. OPERATING MODE
OPERATING
MODE
DMUX Mode
SELECT
VCC
MAXIMUM
CONVERSION RATE
DATA OUTPUT
120MSPS
Demultiplexed Output 60 MBPS
CLOCK OUTPUT
The input clock is 1/2 frequency divided and output at
60MHz.
Straight Mode GND
100MSPS
Straight Output 100 MBPS
The input clock is inverted and output at 100MHz.
DMUX Mode (See Application Circuits,
Figures 18, 19)
Set the SELECT pin to VCC for this mode. In this mode, the
clock frequency is divided by 2 in the IC, and the data is
output after being
divided clock. The
demultiplexed
1/2 frequency
by this 1/2 frequency
divided clock, which has
adequate setup time and hold time for the output data, is
output from the CLKOUT pin.
When using multiple HI3246 units in parallel in this mode,
differences in the start timing of the 1/2 frequency divided clock
may cause operation as shown in Figure 9. As a
countermeasure, the HI3246 is equipped with a function which
resets the 1/2 frequency divided clock. When resetting this
clock, the RESET pulse must be input to the RESET pin. See
the Timing Charts for the RESET pulse input timing. The A/D
converter can operate at fC (Min) = 120MSPS in this mode.
Straight Mode (See Application Circuits, Figures
20, 21)
Set the SELECT pin to GND for this mode. In this mode, data
output can be obtained in accordance with the clock frequency
applied to the A/D converter for applications which use the
clock applied to the A/D converter as the system clock.
The A/D converter can operate at fC (Min) = 100MSPS in
this mode.
Digital Input Level and Supply Voltage Settings
The logic input level for the HI3246 supports PECL and TTL
levels.
The power supplies (DVEE3, DGND3) for the logic input
block must be set to match the logic input (CLK and RESET
signals) level.
10
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