ADC-304 데이터 시트보기 (PDF) - DATEL Data Acquisition products
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ADC-304 Datasheet PDF : 5 Pages
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ADC-304
4. The voltage between VT and VB is equivalent to the dynamic
range of the analog input. Bypass VB to ANALOG GND
USING a 1µF and a 0.01µF capacitor in parallel. To balance
the characteristics of the ADC-304 at high frequencies,
bypass VM with a 0.01µF capacitor to ANALOG GND.
Also, VM can be used as a trimming pin for more precise
linearity compensation. A stable voltage source with a
potential equal to VB and a 1kΩ potentiometer can be
connected to VM as shown in Figure 2 for this purpose.
5. Separate the clock input, CLOCK, from other leads as much
as possible, observing proper EMI and RFI wiring
techniques. This reduces the inductive pick-up of this lead
from interfering with the “clean” operation of the ADC-304.
6. The analog input signal is sampled on the positive-going
edge of CLOCK. Corresponding digital data appears at the
output on the negative-going edge of the CLOCK pulse after
a brief delay of 31ns maximum (TDLH, TDHL). Refer to the
Timing Diagram (Figure 3) for more information.
7. Connect all free pins to ANALOG GND to reduce unwanted
noise.
The analog input range is equal to a 2V spread. The
voltage on VT-VB will equal 2V. The connection of VT and
ANALOG GND is 2V higher than VB. Whether using a
single or dual power supply, the analog input will range from
the value of VT to VB. If VT equals +5V, then VB will equal
+3V and the analog input range will be from +3 to +5V.
+5V
ADC-304
0.01µF
ANA GND
1kΩ
VB
VB
VM
0.01µF
SINGLE SUPPLY OPERATION
ADC-304
ANA GND
VB
VB
1kΩ
VM
0.01µF
DUAL SUPPLY OPERATION
Figure 2.
Improving Linearity Compensation
Ta
N(1)
N(2)
N(3)
ANALOG
INPUT
TPW1
TPW0
CLOCK
COMPARATOR
OUTPUT
6-BIT LATCH OUTPUT
DATA OUTPUT
BITS 1-8
N DATA VALID
N(1) DATA VALID
TDLH
22ns
max.
TDHL
31ns max.
TDLH
22ns
max.
TDHL
31ns max.
N(2) DATA VALID
Figure 3. ADC-304 Timing Diagram
3
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