HI1171 데이터 시트보기 (PDF) - Intersil
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HI1171 Datasheet PDF : 7 Pages
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HI1171
Absolute Maximum Ratings
Thermal Information
Digital Supply Voltage DVDD to DVSS . . . . . . . . . . . . . . . . . . +7.0V
Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . +7.0V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
Maximum Junction Temperature, Plastic Package . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = +4.75V to +5.25V,
CLK Pulse Width = 12.5ns,
DTVAD=D2=5o+C4.(7N5ottoe
+5.25V,
4)
VREF
=
+2.0V,
fS
=
40MHz,
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
SYSTEM PERFORMANCE
Resolution, n
-
8
-
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, VOS
Full Scale Error, FSE (Adjustable to Zero)
fS = 40MHz (End Point)
fS = 40MHz
(Note 2)
(Note 2)
-0.5
-
1.3
-
-
±0.25
-
-
1
-
-
±13
Full Scale Output Current, IFS
Full Scale Output Voltage, VFS
Output Voltage Range, VFSR
DYNAMIC CHARACTERISTICS
-
10
15
1.9
2.0
2.1
0.5
2.0
2.1
Throughput Rate
See Figure 7
40.0
-
-
Glitch Energy, GE
Differential Gain, ∆AV (Note 3)
Differential Phase, ∆φ (Note 3)
ROUT = 75Ω
-
30
-
-
1.2
-
-
0.5
-
REFERENCE INPUT
Voltage Reference Input Range
0.5
-
2.0
Reference Input Resistance
(Note 3)
1.0
-
-
DIGITAL INPUTS
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic Current, IIL, IIH
Digital Input Capacitance, CIN
TIMING CHARACTERISTICS
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.0
-
-
-
-
1.5
-
-
±5.0
-
5.0
-
Data Setup Time, tSU
Data Hold Time, tHLD
See Figure 1
See Figure 1
5
-
-
10
-
-
UNITS
Bits
LSB
LSB
mV
LSB
mA
V
V
MHz
pV-s
%
Degree
V
MΩ
V
V
µA
pF
ns
ns
3
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