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HI1171 데이터 시트보기 (PDF) - Intersil

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HI1171 Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
Typical Performance Curves
2
HI1171
200
100
1
VDD = 5.0V, R = 200
16R = 3.3k, TA = 25oC
1
2
REFERENCE VOLTAGE (V)
FIGURE 2. OUTPUT FULL SCALE VOLTAGE vs REFERENCE
VOLTAGE
100
200
OUTPUT RESISTANCE ()
FIGURE 3. OUTPUT RESISTANCE vs GLITCH ENERGY
2.0
1.9
VDD = 5.0V, VREF = 2.0V
R = 200Ω, 16R = 3.3k
TA = 25oC
0
-25
0
25
50
75
AMBIENT TEMPERATURE (oC)
FIGURE 4. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE
Pin Descriptions
24 PIN
SOIC
1-8
9
10, 13
11
12
14
15
16
PIN
NAME
PIN DESCRIPTION
D0(LSB) thru Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit.
D7(MSB)
BLNK
Blanking Line, used to clear the internal data register to the zero condition when High, normal operation
when Low.
DVSS
VB
CLK
Digital Ground.
Voltage Bias, connect a 0.1µF capacitor to DVSS.
Data Clock Pin 100kHz to 40MHz.
AVSS
IREF
VREF
Analog Ground.
Current Reference, used to set the current range. Connect a resistor to AVSS that is 16 times greater
than the resistor on IOUT1. (See Typical Applications Circuit).
Input Reference Voltage used to set the output full scale range.
5

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