HI5714(1998) 데이터 시트보기 (PDF) - Intersil
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HI5714 Datasheet PDF : 13 Pages
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HI5714
Detailed Description
Theory of Operation
The HI5714 design utilizes a folding and interpolating
architecture. This architecture reduces the number of com-
parators, reference taps, and latches, thereby reducing
power requirements, die size and cost.
A folding A/D converter operates basically like a 2 step
subranging converter by using 2 lower resolution converters
to do a course and subranged fine conversion. A more com-
plete description is given in the application note “Using the
HI5714 Evaluation Module” (AN9517).
Reference Input, VRT and VRB
The HI5714 requires an external reference to be connected
to pins 4 and 9, VRB and VRT.
It is recommended that adequate high frequency decoupling
be provided at the reference input pin in order to minimize
overall converter noise. A 0.1µF and a 1nF capacitor as
close as possible to the reference pins work well.
VRT must be kept within the range of 3.5V to 3.9V and VRB
within 1.2V to 1.6V. If the reference voltages go outside their
respective ranges, the input folding amplifiers may saturate
giving erroneous digital data. The range for (VRT - VRB) is
1.9V to 2.7V, which defines the analog input range.
Digital Control and Clock Requirements
The HI5714 provides a standard high-speed interface to
external TTL logic families.
The outputs can be three-stated by setting the OE input (pin
22) high.
The clock input operates at standard TTL levels as well as a low
level sine wave around the threshold level. The HI5714 can oper-
ate with clock frequencies from DC to 75MHz. The clock duty
cycle should be 50% ±10% to ensure rated performance. Duty
cycle variation, within the specified range, has little effect on per-
formance. Due to the clock speed it is important to remember
that clock jitter will affect the quality of the digital output data.
The clock can be stopped at any time and restarted at a later
time. Once restarted the digital data will be valid at the
second rising edge of the clock plus the data delay time.
Digital Outputs and O/UF Output
The digital outputs are standard TTL type outputs. The
HI5714 can drive 1 to 3 TTL inputs depending on the input
current requirements.
Should the analog input exceed the top or bottom reference
the over/underflow output (pin 11) will go high. Should the
analog input exceed the top reference voltage, VRT, the
digital outputs will remain at all 1s until the analog input goes
below VRT. Also, should the analog input go below the bot-
tom reference voltage, VRB, the digital outputs will remain at
all 0s until the analog input goes above VRT.
Analog Input
The analog input will accept a voltage within the reference
voltage levels, VRB and VRT, minus some offset. The offset is
specified in the Electrical Specifications table.
The analog input is relatively high impedance (10kΩ) but
should be driven from a low impedance source. The input
capacitance is low (14pF) and there is little kickback from the
input, so a series resistance is not necessary but it may help
to prevent the driving amplifier from oscillating.
The input bandwidth is typically 18MHz. Exceeding 18MHz
will result in sparkle at the digital outputs. The bandwidth
remains constant at clock rates up to 75MHz.
Supply and Ground Considerations
In order to keep digital noise out of the analog signal path,
the HI5714 has separate analog and digital supply and
ground pins. The part should be mounted on a board that
provides separate low impedance connections for the analog
and digital supplies and grounds.
The analog and digital grounds should be tied together at
one point near the HI5714. The grounds can be connected
directly, through an inductor (ferrite bead), or a low valued
resistor. DGND and AGND can be tied together. To help min-
imize noise, tie pin 5 (NC) to AGND and pins 3 (NC) and 10
(NC) to DGND.
For best performance, the supplies to the HI5714 should be
driven by clean, linear regulated supplies. The board should
also have good high frequency leaded decoupling capacitors
mounted as close as possible to the converter. Capacitor
leads must be kept as short as possible (less than 1/2 inch
total length). A 0.1µF and a 1nF capacitor as close as possi-
ble to the pin works well. Chip capacitors will provide better
high frequency decoupling but leaded capacitors appear to
be adequate.
If the part is to be powered by a single supply, then the
analog supply pins should be isolated by ferrite beads from
the digital supply pins. This should help minimize noise on
the analog power pins.
Refer to Application Note AN9214, “Using Intersil High
Speed A/D Converters”, for additional considerations when
using high speed converters.
Increased Accuracy
Further calibration of the ADC can be done to increase
absolute level accuracy. First, a precision voltage equal to
the ideal VIN-FS + 0.5 LSB is applied at VIN. Adjust VRB
until the 0 to 1 transition occurs on the digital output. Next, a
voltage equal to the ideal VIN+FS - 1.5 LSB is applied at VIN.
VRT is then adjusted until the 254 to 255 transition occurs on
the digital output.
Applications
Figures 3 and 4 show two possible circuit configurations, AC
coupled with a DC restore circuit and DC coupled with a DC
offset amplifier.
Due to the high clock rate, FCT (TTL/CMOS) or FAST (TTL)
glue logic should be used. FCT logic will tend to have large
overshoots if not loaded. Long traces (>2 or 3 inches) should
be terminated to maintain signal integrity.
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