PM3386-BI 데이터 시트보기 (PDF) - PMC-Sierra

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PM3386-BI

DUAL GIGABIT ETHERNET CONTROLLER

PMC-Sierra 

RELEASED

DATASHEET

PMC-1991129

ISSUE 7

PM3386

DUAL GIGABIT ETHERNET CONTROLLER

Management Statistics (MSTAT)

The PM3386 also incorporates a rich set of per port RMON, SNMP, and Etherlike

Management Information Base counters. Deep statistical counters are used for

management counts providing a minimum rollover time of greater than 58

minutes. All counts are easily managed via the Management Statistics (MSTAT)

block.

POS-PHY Level 3 Interface (PL3)

The PM3386 can connect to a single upper layer device through a POS-PHY

Level 3 Interface. The POS-PHY Level 3 interface is a 32-bit wide interface with

a clock rate from 60 to 104 MHz. POS-PHY Level 3 was developed with the

cooperation of the SATURN Development Group to cover all application bit rates

up to and including 3.2 Gbit/s. This interface provides standards support for

interoperation between the PM3386, a multiple PHY layer device, connecting to

one Link Layer device. The interface stresses simplicity of operation to allow

forward migration to more elaborate PHY and Link Layer devices. The POS-

PHY interface contains 64KB receive and 16KB transmit FIFOs per channel.

These FIFOs contain programmable thresholds specifying full and empty

conditions.

Receive Direction

In the receive direction, the PM3386 can be configured to use the internal

SERDES or the GMII interface on a per channel basis. For SERDES operation,

a Gigabit Ethernet bit stream is received from an external optical transceiver.

The data is recovered and converted from serial to parallel data for connection to

the EGMAC block. The EGMAC terminates the 8B/10B line codes and performs

frame integrity checks (frame length, FCS etc). For GMII operation, the physical

packet is sourced from an external copper physical layer device to the PM3386

via the GMII interface (8 bits clocked at 125 MHz). The EGMAC accepts the 8 bit

data and performs frame integrity checks once the complete frame is received.

The EGMAC can optionally filter erred frames.

Statistics are updated and the frame is sent to the POS-PHY Level 3 interface.

The FIFO’s in the POS-PHY interface accommodate system latencies and allows

for loss-less flow control up to 9.6k bytes. The received frames are then read

through the POS-PHY Level 3 (32 bits clocked from 60-104 MHz) system side

interface.

Transmit Direction

In the transmit direction, packets to be transmitted are written into the POS-PHY

TX FIFO through the POS-PHY Level 3 interface (32 bits clocked from 60-104

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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