PM3386-BI 데이터 시트보기 (PDF) - PMC-Sierra

부품명

상세내역

제조사

PM3386-BI

DUAL GIGABIT ETHERNET CONTROLLER

PMC-Sierra 

RELEASED

DATASHEET

PMC-1991129

ISSUE 7

PM3386

DUAL GIGABIT ETHERNET CONTROLLER

MHz) from the upper layer device. The channel is selected by the upper layer

device and is indicated in-band on the POS-PHY interface. The EGMAC builds a

properly formatted Ethernet physical packet (padding to minimum size and

inserting the preamble, start of frame delimiter (SFD) and the inter-packet gap

(IPG)). Statistics are updated and the physical packet is sent to the SERDES or

the GMII interface.

For SERDES operation, the EGMAC encodes the physical packet using 8B/10B

encoding and passes the physical packet to the SERDES block. The SERDES

performs parallel to serial conversion using an internally synthesized 1250 MHz

clock. The bit stream is sent to an external optical transceiver for transmission

over fiber cable. For GMII operation, the EGMAC sends the physical packet byte

by byte across the GMII interface (8 bits clocked at 125 MHz) to an external

copper Gigabit Ethernet physical layer device. The copper Gigabit Ethernet

physical layer device then transmits the physical packet over copper cable.

Flow Control

Flow control is handled in the EGMAC block. When a PAUSE control frame is

received, the PM3386 will optionally terminate transmission (after the current

frame is sent) and assert the appropriate channel side band flow control output

to indicate the paused condition. The received PAUSE control frame can be

optionally filtered or passed to the link layer device via the POS-PHY Level 3

interface.

PAUSE control frames are transmitted either under link layer control using

channel side band flow control inputs, under link layer control transparent to the

PM3386, host based PAUSE frame control or under internal control based on

receive FIFO levels. All four methods can provide for loss-less flow control.

General

The PM3386 is configured, controlled and monitored via a generic 16-bit

microprocessor bus interface. The PM3386 also provides a standard 5 signal

IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The PM3386 is implemented in low power, +1.8 Volt, CMOS technology with 5V

TTL compatible digital inputs and 3.3V TTL/CMOS compatible digital outputs.

The PM3386 is packaged in a 352-pin UBGA package.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

14

Share Link: