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PM73121

AAL1 Segmentation And Reassembly Processor

PMC-Sierra 

Data Sheet

PMC-980620

,VVXH 

PMC-Sierra, Inc.

PM73121 AAL1gator II

AAL1 SAR Processor

From Version

01/21/98

To Version

04/17/98

10/17/97

(first version of the

WAC-121-A

User’s Manual)

01/21/98

Major Changes

• Under section 6.5.1 “RAM Timing” starting on page 103, changed

from “12 ns or 15 ns SRAMs” to “12 ns SRAMs”, changed from

“data setup time of 8 ns” to “data setup time of 7 ns”, and changed

from “SYS_CLK is 38.88 MHz” to “SYS_CLK is 40 MHz”.

• In the table after Figure 80 on page 119, changed the Fc maximum

value from “38.89” to “40.00”.

• Under “QUEUE_CONFIG Word Format” section starting on

page 135, added the second and third bullet to the note for the

“FRAMES_PER_CELL” description and the note for the

“BYTES_PER_CELL” description.

• Under section 7.8.6 “R_CH_TO_QUEUE_TBL”, on page 148,

added the sixth sentence to the Function description.

• Under section 8.6 “Board Requirements for the SRAM Interface”

starting on page 174, changed the third paragraph from “SRAMs

must be 15 ns or faster” to “SRAMS must be 12 ns or faster”,

changed from “data setup of 8 ns” to “data setup of 7 ns” and

deleted the following four sentences.

• Added section 8.7 “UDF-HS Mode SRTS-Based Clock Recovery

Application for DS3” starting on page 180, section 8.8

“Interfacing with the Mitel MT8980 Digital Switch”, on page 182,

section 8.9 “Interfacing with the ATM Cell Multiplexer (WAC-

185-B-X)”, on page 183, and section 8.10 “Jitter Characteristics

of Clock Synthesis Logic” on page 185.

• In the first sentence under “Description” on page 1, added E3 to

the list of lines supported.

• Under section 2.2 “Circuit Interface Features” starting on page 16,

added the Dallas Semiconductor part DS2152 to the second bullet,

added the Dallas Semiconductor part DS2154 to the third bullet,

deleted the IgT DS3 Framer (TAC-030-A), and deleted the Dallas

part number DS2180A.

• Under section 2.4 “Receive Interface Features” on page 18,

changed the fourth bullet text from “0 to 48 ms” to “0 to 24 ms”.

• Under section 2.5 “Statistics” starting on page 19, deleted text

from the fourth bullet and added the fourth sentence in the first

paragraph on page 20.

• Under section 2.7 “SRTS and Transmit Line Interface Clock

Configurations” on page 21, and section 3.1. “SRTS for the

Transmit Side” added the NOTE regarding Bellcore’s SRTS

patent.

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